XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 73
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 73 of 385
- Download datasheet (14Mb)
Connecting DCMs to Other Clock Resources in Virtex-5 Devices
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Dynamic Reconfiguration
IBUFG to DCM
DCM to BUFGCTRL
BUFGCTRL to DCM
The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without
reloading a new bit stream to the FPGA. The DRP address mapping changed in Virtex-5
FPGAs. The Virtex-5 FPGA Configuration Guide provides more information on using DRPs.
Specific to the DCM, DRPs allow dynamic adjustment of the CLKFX_MULTIPLY(M) and
CLKFX_DIVIDE(D) values to produce a new CLKFX frequency.
The following steps are required when using DRPs to load new M and D values:
•
•
•
•
Most DCM functions require connection to dedicated clock resources, including dedicated
clock I/O (IBUFG), clock buffers (BUFGCTRLs), and PLLs. These clock resources are
located in the center column of the Virtex-5 devices. This section provides guidelines on
connecting the DCM to dedicated clock resources.
Virtex-5 devices contain 20 clock inputs. These clock inputs are accessible by instantiating
the IBUFG. Each top and bottom half of a Virtex-5 device contains 10 IBUFGs. Any of the
IBUFG in top or bottom half of the Virtex-5 device can drive the clock input pins (CLKIN,
CLKFB, PSCLK, or DCLK) of a DCM located in the same top/bottom half of the device.
Any DCM clock output can drive any BUFGCTRL input in the same top/bottom half of
the device. There are no restrictions on how many DCM outputs can be used
simultaneously.
Any BUFGCTRL can drive any DCM in the Virtex-5 devices. However, only up to ten
dedicated clock routing resources exist in a particular clock region. Since the clock routing
is accessed via the BUFGCTRL outputs, this indirectly limits the BUFGCTRL to DCM
connection. If ten BUFGCTRL outputs are already accessing a clock region, and a DCM is
in that region, then no additional BUFGCTRL can be used in that region, including a
connection to the CLKFB pin of the DCM.
Subtract the desired M and D values by one. For example, if the desired M/D = 9/4,
then load M/D = 8/3.
Hold DCM in reset (assert RST signal) and release it after the new M and D values are
written. The CLKFX outputs can be used after LOCKED is asserted High again.
Read DADDR0 to restore the default status on D0.
Release RST.
Connecting DCMs to Other Clock Resources in Virtex-5 Devices
www.xilinx.com
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