XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 227
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 227 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Driver with Termination to V
Figure 6-11
X-Ref Target - Figure 6-11
Some I/O standards (e.g., HSTL Class IV) require an output termination to V
Figure 6-12
X-Ref Target - Figure 6-12
DCI can provide an output termination to V
only controls the impedance of the termination, but not the driver. Both GTL and HSTL
standards need 50 Ω external reference resistors. The DCI I/O standards supporting
drivers with single termination are: GTL_DCI, GTLP_DCI, HSTL_IV_DCI, and
HSTL_IV_DCI_18.
Figure 6-11: Input Termination to V
illustrates split termination inside a Virtex-5 device.
illustrates an output termination to V
Figure 6-12: Driver with Termination to V
www.xilinx.com
Virtex-5 FPGA
CCO
Z
0
(Single Termination)
IOB
Virtex-5 DCI
IOB
V
CCO
2R
2R
CCO
V
CCO
CCO
SelectIO Resources General Guidelines
V
using single termination. In this case, DCI
R
CCO
REF
/2 Using DCI Split Termination
UG190_c6_10_022609
UG190_6_09_021206
.
Z
0
CCO
without DCI
CCO
.
227
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