XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 217
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 217 of 385
- Download datasheet (14Mb)
SelectIO Resources
I/O Tile Overview
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Input/output characteristics and logic resources are covered in three consecutive chapters.
Chapter 6, SelectIO Resources
input receivers, and gives detailed examples of many standard interfaces.
SelectIO Logic
Data-Rate (DDR) operation, and the programmable input delay (IDELAY).
Advanced SelectIO Logic
An I/O tile contains two IOBs, two ILOGICs, two OLOGICs, and two IODELAYs.
Figure 6-1
X-Ref Target - Figure 6-1
shows a Virtex-5 FPGA I/O tile.
Resources, describes the input and output data registers and their Double-
(Chapter 7)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
OSERDES
OSERDES
www.xilinx.com
Resources, describes the data serializer/deserializer (SERDES).
ISERDES
ISERDES
IODELAY
IODELAY
OLOGIC
OLOGIC
Figure 6-1: Virtex-5 FPGA I/O Tile
ILOGIC
ILOGIC
or
or
or
or
describes the electrical behavior of the output drivers and
(Chapter 6)
(Chapter 6)
IOB
IOB
ug190_6_01_041106
Pad
Pad
Chapter 6
Chapter 7,
Chapter 8,
217
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