XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 74
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
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- Download datasheet (14Mb)
Chapter 2: Clock Management Technology
74
PLL To and From DCM
DCM To and From PMCD
Figure 2-7
same CMT block. The PLL can drive either DCM in the same CMT block using a dedicated
connection. Similarly, the DCM can drive the PLL within the same CMT block with a
dedicated connection. There is no BUFGCTRL required between the PLL and the DCM.
X-Ref Target - Figure 2-7
The PMCD block is not available in the Virtex-5 devices. However, a limited retargeting
using the PLL is possible. Refer to
for more information.
From any IBUFG implementation
From any BUFG implementation
summarizes the dedicated connection between the DCM and the PLL in the
Figure 2-7: DCM and PLL Connection in Same CMT Block
www.xilinx.com
PLL in Virtex-4 FPGA PMCD Legacy Mode in Chapter 3
PLL to DCM Input
CLKFBIN
PLL to DCM Input
CLKFB
DCM to PLL Input
CLKIN
DCM to PLL Input
CLKFB
CLKIN
CLKIN
DCM2
DCM1
PLL
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Routing (BUFG)
Routing (BUFG)
Routing (BUFG)
To Global
ug190_2_07_072307
To Global
To Global
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