M29W128GH70ZA6E NUMONYX, M29W128GH70ZA6E Datasheet - Page 69

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M29W128GH70ZA6E

Manufacturer Part Number
M29W128GH70ZA6E
Description
Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 70ns 64-Pin TBGA Tray
Manufacturer
NUMONYX
Datasheet

Specifications of M29W128GH70ZA6E

Package
64TBGA
Cell Type
NOR
Density
128 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3|3.3 V
Sector Size
128KByte x 128
Timing Type
Asynchronous
Operating Temperature
-40 to 85 °C
Interface Type
Parallel

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Figure 19. Chip enable controlled program waveforms (8-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see
4. See
of status register data polling bit.
and
Table 26: Read AC characteristics
Table 27: Write AC characteristics, write enable
DQ0-DQ7
A0-A22/
A–1
W
G
E
for details on the timings.
tAVAV
tWLEL
tGHEL
tDVEH
tELEH
3rd cycle
tAVEL
555h
controlled,
AOh
4th cycle
tEHWH
tEHDX
PA
Table 28: Write AC characteristics, chip enable controlled
tEHEL1
PD
Section 7.2.1: Data polling bit
tELAX
tWHWH1
Data Polling
PA
DQ7 D OUT
AI13334
(DQ7)).
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