LH28F640BFHE-PBTL70A Sharp Microelectronics, LH28F640BFHE-PBTL70A Datasheet - Page 7

• Manufacturer Part Number: LH28F640BFHE-PBTL70A
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 70ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F640BFHE-PBTL70A

• Package: 48TSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

DQ
Symbol
A
RST#
V
GND
WE#
WP#
OE#
CE#
V
V
0
0
CCQ
-A
-DQ
CC
PP
21
15
INPUT/SUPPLY
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses. 64M: A
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and partition configuration register code reads. Data pins float to high-
impedance (High Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (V
standby levels.
RESET: When low (V
which provides data protection. RST#-high (V
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WRITE PROTECT: When WP# is V
or program operation can be executed to the blocks which are not locked and not locked-
down. When WP# is V
MONITORING POWER SUPPLY VOLTAGE: V
With V
cannot be executed and should not be attempted.
Applying 9.5V±0.5V to V
mode, V
only be done for a maximum of 1,000 cycles on each block. V
9.5V±0.5V for a total of 80 hours maximum. Use of this pin at 9.5V beyond these limits
may reduce block cycling capability or cause permanent damage.
DEVICE POWER SUPPLY (2.7V-3.6V): With V
flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
GROUND: Do not float any ground pins.
PP
PP
≤V
is power supply pin. Applying 9.5V±0.5V to V
PPLK
Table 1. Pin Descriptions
, block erase, full chip erase, (page buffer) program or OTP program
LHF64FG8
IL
IH
), RST# resets internal automation and inhibits write operations
, lock-down is disabled.
IH
PP
) deselects the device and reduces power consumption to
provides fast erasing or fast programming mode. In this
Name and Function
IL
, locked-down blocks cannot be unlocked. Erase
IH
0
PP
CC
-A
) enables normal operation. After
is not used for power supply pin.
≤V
21
LKO
PP
, all write attempts to the
during erase/program can
PP
CC
may be connected to
voltage (see DC
Rev. 2.45
4