LH28F640BFHE-PBTL70A Sharp Microelectronics, LH28F640BFHE-PBTL70A Datasheet - Page 30

• Manufacturer Part Number: LH28F640BFHE-PBTL70A
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 70ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F640BFHE-PBTL70A

• Package: 48TSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

DQ
DQ
DQ
RST#
RST#
RST#
1.2.6 Reset Operations
NOTES:
1. A reset time, t
2. t
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
5. When the device power-up, holding RST# low minimum 100ns is required after V
t
t
t
t
V
PLPH
PLRH
2VPH
VHQV
Characteristics - Read-Only Operations for t
the reset will complete within 100ns.
also has been in stable there.
CC
15-0
15-0
15-0
Symbol
PLPH
(D/Q)
(D/Q)
(D/Q)
(P)
(P)
(P)
V
is <100ns the device may still reset but this is not guaranteed.
CC
V
V
GND
V
V
V
V
V
V
V
V
V
V
OH
OH
(min)
OH
OL
OL
OL
IH
IL
IH
IL
IH
IL
RST# Low to Reset during Read
(RST# should be low during power-up.)
RST# Low to Reset during Erase or Program
V
V
CC
CC
PHQV
2.7V to RST# High
2.7V to Output Delay
, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Reset AC Specifications (V
High Z
High Z
High Z
Parameter
Figure 11. AC Waveform for Reset Operations
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RST# rising timing
PHQV
.
t
t
PLPH
PLPH
LHF64FG8
CC
t
PLRH
=2.7V-3.6V, T
COMPLETE
t
ABORT
2VPH
1, 2, 3
1, 3, 4
1, 3, 5
Notes
A
=-40°C to +85°C)
3
SR.7="1"
t
PHQV
t
VHQV
CC
Min.
100
100
has been in predefined range and
t
PHQV
t
PHQV
Max.
22
1
OUTPUT
VALID
Rev. 2.45
OUTPUT
VALID
Unit
ms
µs
ns
ns
OUTPUT
VALID
27