LH28F640BFHE-PBTL70A Sharp Microelectronics, LH28F640BFHE-PBTL70A Datasheet - Page 23

• Manufacturer Part Number: LH28F640BFHE-PBTL70A
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 70ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F640BFHE-PBTL70A

• Package: 48TSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V
2. I
3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
5. Sampled, not 100% tested.
6. V
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
8. For all pins other than those shown in test conditions, input level is V
V
V
V
V
V
V
V
V
Symbol
IL
IH
OL
OH
PPLK
PPH1
PPH2
LKO
unless V
erase suspend mode, the device’s current draw is the sum of I
buffer) program suspend mode, the device’s current draw is the sum of I
in the range between V
completion. Standard address access timings (t
program cannot be executed and should not be attempted.
Applying 9.5V±0.5V to V
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths
and layout considerations given to the V
Applying 9.5V±0.5V to V
may be connected to 9.5V±0.5V for a total of 80 hours maximum.
CCWS
PP
is not used for power supply pin. With V
and I
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
Erase, (Page Buffer) Program or OTP
Program Operations
V
Erase, (Page Buffer) Program or OTP
Program Operations
V
Operations
CC
PP
PP
PP
CC
is specified.
Lockout during Normal
CCES
Lockout Voltage
during Block Erase, Full Chip
during Block Erase, Full Chip
are specified with the device de-selected. If read or (page buffer) program is executed while in block
Parameter
PPLK
PP
PP
(max.) and V
provides fast erasing or fast programming mode. In this mode, V
during erase/program can only be done for a maximum of 1,000 cycles on each block. V
CC
PPH1
DC Characteristics (Continued)
power bus.
(min.), between V
AVQV
PP
≤V
Notes
3,5,6
V
) provide new data when addresses are changed.
LHF64FG8
5
5
5
5
6
6
CC
PPLK
=2.7V-3.6V
, block erase, full chip erase, (page buffer) program and OTP
V
Min.
1.65
-0.4
-0.2
2.4
9.0
1.5
CCQ
CCES
PPH1
and I
(max.) and V
CCQ
Typ.
3.0
9.5
CCWS
CCR
or GND.
or I
and I
V
Max.
+ 0.4
10.0
0.4
0.2
0.4
3.6
CCQ
CCW
PPH2
CCR
. If read is executed while in (page
(min.) and above V
.
Unit
V
V
V
V
V
V
V
V
PP
≤V
PP
CC
PPLK
V
V
I
V
V
I
OL
OH
is power supply pin and
CC
CCQ
CC
CCQ
=3.0V and T
=100µA
=-100µA
Test Conditions
=V
=V
, and not guaranteed
=V
=V
CC
CC
CCQ
CCQ
PPH2
Min.,
Min.,
Min.,
Min.,
Rev. 2.45
(max.).
A
=+25°C
20
PP