DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 92

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Manual Error Insert Mode Select (MEIMS). When 0, the transmit manual error insertion signal (TMEI) will
not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a
1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0].
Bits 6 to 0: Transmit Errored Packet Insertion Rate (TPER6 to TPER0). These seven bits indicate the rate at
which errored packets are to be output. One out of every x * 10
the value x, and TPER[6:4] is the value y which has a maximum value of 6. If TPER[3:0] has a value of 0h errored
packet insertion is disabled. If TPER[6:4] has a value of 6xh or 7xh the errored packet rate is x * 10
value of 01h results in every packet being errored. A TPER[6:0] value of 0Fh results in every 15
errored. A TPER[6:0] value of 11h results in every 10
To initiate automatic error insertion, use the following routine:
Cleanup routine:
1) Write LI.TEPLC and LI.TEPHC each to 00h.
2) Write the LI.TPPCL.TIAEI bit to 0.
1)
2)
3)
LI.TPPSR.TEPF bit for completion of the error insertion. If interrupt on completion of error insertion is enabled
(LI.TPPSRIE.TEPFIE = 1), the user only needs to wait for the interrupt condition.
4)
Configure LI.TEPLC and LI.TEPHC for the desired error insertion mode.
Write the LI.TPPCL.TIAEI bit to 1. Note that this bit is write-only.
If not using continuous error insertion (LI.TPELC is not equal to FFh), the user should monitor the
Proceed with the cleanup routine listed below.
MEIMS
7
0
TPER6
6
0
LI.TEPHC
Transmit Errored Packet High Control Register
0C7h
TPER5
5
0
TPER4
92 of 167
th
packet being errored.
4
0
y
TPER3
packets is to be an errored packet. TPER[3:0] is
3
0
TPER2
2
0
TPER1
1
0
th
6
. A TPER[6:0]
packet being
TPER0
0
0