DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 76

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit Sync Latched Status 4 (ITSYNCLS4). This is a latched status bit for ITSYNC4.
Bit 6: IMUX Transmit Sync Latched Status 3 (ITSYNCLS3). This is a latched status bit for ITSYNC3.
Bit 5: IMUX Transmit Sync Latched Status 2 (ITSYNCLS2). This is a latched status bit for ITSYNC2.
Bit 4: IMUX Transmit Sync Latched Status 1 (ITSYNCLS1). This is a latched status bit for ITSYNC1.
Bit 3: IMUX Receive Sync Latched Status 4 (IRSYNCLS4). This is a latched status bit for IRSYNC4.
Bit 2: IMUX Receive Sync Latched Status 3 (IRSYNCLS3). This is a latched status bit for IRSYNC3.
Bit 1: IMUX Receive Sync Latched Status 2 (IRSYNCLS2). This is a latched status bit for IRSYNC2.
Bit 0: IMUX Receive Sync Latched Status 1 (IRSYNCLS1). This is a latched status bit for IRSYNC1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0 IMUX Differential Delay. These 8 bits provide the IMUX differential delay. The maximum differential
delay that can be measured is 64ms.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: IMUX Differential Delay Error Interrupt Enable (IDDEIE). Setting this bit to 1 enables an interrupt on
IDDELS0.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: IMUX Differential Delay Error latched Status (IDDELS0). This bit provides the differential delay error
latched status. It is set to 1 when the differential delay has exceeded 7.75ms.
ITSYNCLS4
IMUXDFD7
—
—
7
0
7
0
7
0
7
0
ITSYNCLS3
IMUXDFD6
—
—
0
0
6
6
6
0
6
0
GL.IMXSLS
Inverse MUX Sync Latched Status
1Ah
GL.IMXDFD
Inverse MUX Diff Delay
1Bh
GL.IMXDFEIE
Inverse MUX Diff Delay Error Interrupt Enable
1Ch
GL.IMXDFDELS
Inverse MUX Diff Delay Error Latched Status
1Dh
ITSYNCLS2
IMUXDFD5
—
—
5
0
5
0
5
0
5
0
ITSYNCLS1
IMUXDFD4
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—
—
4
0
4
0
4
0
4
0
IRSYNCLS4 IRSYNCLS3 IRSYNCLS2 IRSYNCLS1
IMUXDFD3
—
—
3
0
3
0
3
0
3
0
IMUXDFD2
—
—
2
0
2
0
2
0
2
0
IMUXDFD1
—
—
1
0
1
0
1
0
1
0
IDDELS0
IDDEIE
IMUXDFD0
0
0
0
0
0
0
0
0