DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 22

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33Z41 Quad IMUX Ethernet Mapper
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FUNCTIONAL DESCRIPTION
The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86(LAPS) Mapper,
SDRAM interface, Serial IBO interface, control ports, and Bit Error Rate Tester (BERT).
The Ethernet Packet interfaces support MII and RMII interfaces allowing DSZ33Z41 to connect to commercially
available Ethernet PHY and MAC devices. The Ethernet interfaces can be individually configured for 10Mbps or
100Mbps service, in DTE and DCE configurations. The DS33Z41 MAC interface can be configured to reject
frames with bad FCS and short frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33Z41 SDRAM controller enables
connection to a 128Mbit SDRAM without external glue logic, at clock frequencies up to 100MHz. The SDRAM is
used for both the Transmit and Receive Data Queues. The Receive Queue stores data to be sent from the Packet
interface to the WAN interface. The Transmit Queue stores data to be sent from the WAN interface to the Packet
interface. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.
The sizing of the queues can be adjusted by software. The user can also program high and low watermarks for
each queue that can be used for automatic or manual flow control. The packet data stored in the SDRAM is
encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interfaces. The device also provides the
capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN physical interface supports up to four serial data streams on a 8.192Mbps IBO bus. The
WAN serial port can operate with a gapped clock, and can be connected to a framer or T/E-Carrier transceiver for
transmission to the WAN. The WAN interface can be seamlessly connected to the Dallas Semiconductor/Maxim
T1/E1/J1 Framers and Single-Chip Transceivers (SCTs).
The DS33Z41 can be configured through an 8-bit Microprocessor interface port. The DS33Z41 also provides two
on-board clock dividers for the System Clock input and Reference Clock Input for the 802.3 interfaces, further
reducing the need for ancillary devices.
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