DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 78

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit OOF Latched Status 4 (TOOFLS4). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 6: IMUX Transmit OOF Latched Status 3 (TOOFLS3). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 5: IMUX Transmit Sync Latched Status 2 (TOOFLS2). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 4: IMUX Transmit Sync Latched Status 1 (TOOFLS1). This is a latched bit for Transmit OOF , this bit is set
if the distant end is out of frame.
Bit 3: IMUX Receive Sync Latched Status 4 (ROOFLS4). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 2: IMUX Receive Sync Latched Status 3 (ROOFLS3). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 1: IMUX Receive Sync Latched Status 2 (ROOFLS2). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 0: IMUX Receive Sync Latched Status 1 (ROOFLS1). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Note that the user must clear the GL.IMXCN.SENDE bit to stop data transmission when an OOF condition is
detected. The user must re-initiate the handshaking procedure for re-establishment of communication.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: BIST Enable (BISTE). If this bit is set the DS33Z41 performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the DS33Z41 after completion of BIST
test before normal dataflow can begin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: BIST DONE (BISTDN). If this bit is set to 1, the DS33Z41 has completed the BIST Test initiated by BISTE.
The pass fail result is available in BISTPF.
TOOFLS4
—
—
7
0
7
0
7
0
OOFLS3
—
—
6
0
6
0
6
0
GL.IMXOOFLS
Inverse MUX Out Of Frame Latched Status
1Fh
GL.BISTEN
BIST Enable
20h
GL.BISTPF
BIST PassFail
21h
TOOFLS2
—
—
5
0
5
0
5
0
TOOFLS1
78 of 167
—
—
4
0
4
0
4
0
ROOFL4
—
—
3
0
3
0
3
0
ROOFL3
—
—
2
0
2
0
2
0
ROOFLS2
BISTDN
—
1
0
1
0
1
0
ROOFLS1
BISTPF
BISTE
0
0
0
0
0
0