DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 129

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
001Ch:
Bit #
Name
Default
001Dh:
Bit #
Name
Default
001Eh:
Bit #
Name
Default
001Fh:
Bit #
Name
Default
Bits 31 to 16: Pause Time (PT15 to PT00). These bits are used for the Pause Time Field in transmitted Pause
Frames. This value is the number of time slots the remote node should wait prior to transmission.
Bit 1: Flow Control Enable (FCE) When set to 1, the MAC automatically detects pause frames and will disable
the transmitter for the requested pause time.
Bit 0: Flow Control Busy (FCB) The host can set this bit to 1 in order to initiate transmission of a pause frame.
During transmission of a pause frame, this bit remains set. The DS33Z41 will clear this bit when transmission of
the pause frame has been completed. The user should read this bit and ensure that this bit is equal to zero prior
to initiating a pause frame.
Reserved
Reserved
PT15
PT07
31
23
15
07
0
0
0
0
Reserved
Reserved
PT14
PT06
30
22
14
06
0
1
0
0
SU.MACFCR
MAC Flow Control Register
001Ch (indirect)
Reserved
Reserved
PT13
PT05
29
21
13
05
0
0
0
0
Reserved
Reserved
129 of 167
PT12
PT04
28
20
12
04
0
1
0
0
Reserved
Reserved
PT11
PT03
27
19
11
03
0
0
0
0
Reserved
Reserved
PT10
PT02
10
26
18
02
0
0
0
0
Reserved
PT09
PT01
FCE
25
17
09
01
0
0
0
1
Reserved
PT08
PT00
FCB
00
24
16
08
0
0
0
0