DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet
DS33Z41
Specifications of DS33Z41
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DS33Z41 Summary of contents
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... GENERAL DESCRIPTION The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over up to four interleaved PDH/TDM data streams using robust, balanced, and programmable inverse multiplexing. The Interleave Bus (IBO) serial link supports seamless bidirectional interconnection with Dallas Semiconductor’ ...
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DESCRIPTION ....................................................................................................................7 2 FEATURE HIGHLIGHTS ....................................................................................................8 2.1 G ......................................................................................................................................8 ENERAL 2 INK GGREGATION NVERSE 2.3 HDLC ...........................................................................................................................................8 2 OMMITTED NFORMATION 2.5 X.86 S ..............................................................................................................................8 UPPORT 2.6 SDRAM I ......................................................................................................................9 NTERFACE 2.7 MAC I ...........................................................................................................................9 ...
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E MAC..........................................................................................................................46 THERNET 8.14.1 MII Mode .............................................................................................................................................47 8.14.2 RMII Mode ..........................................................................................................................................47 8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................48 8.15 BERT .........................................................................................................................................48 8.15.1 BERT Features ...................................................................................................................................48 8.15.2 Receive Data Interface .......................................................................................................................49 8.15.3 Repetitive Pattern Synchronization.....................................................................................................49 8.15.4 Pattern Monitoring...............................................................................................................................50 ...
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BYPASS............................................................................................................................................163 12.2.3 EXTEST ............................................................................................................................................163 12.2.4 CLAMP..............................................................................................................................................163 12.2.5 HIGHZ ...............................................................................................................................................163 12.2.6 IDCODE ............................................................................................................................................163 12.3 JTAG ID C .......................................................................................................................164 ODES 12 ......................................................................................................................164 EST EGISTERS 12.4.1 Boundary Scan Register ...................................................................................................................164 12.4.2 Bypass Register................................................................................................................................164 12.4.3 Identification Register .......................................................................................................................164 12.5 JTAG F ...
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... Figure 8-6. Flow Control Using Pause Control Frame ............................................................................................ 41 Figure 8-7. IEEE 802.3 Ethernet Frame .................................................................................................................. 42 Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode ......................................................... 44 Figure 8-9. DS33Z41 Configured as a DCE in MII Mode ........................................................................................ 45 Figure 8-10. RMII Interface...................................................................................................................................... 47 Figure 8-11. MII Management Frame...................................................................................................................... 48 Figure 8-12 ...
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Table 2-1. T1 Related Telecommunications Specifications .................................................................................... 10 Table 7-1. Detailed Pin Descriptions ....................................................................................................................... 14 Table 8-1. Clock Selection for the Ethernet (LAN) Interface ................................................................................... 24 Table 8-2. Reset Functions ..................................................................................................................................... 27 Table 8-3. Commands Sent and Received on the ...
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... The Ethernet interface can be configured for 10Mbps or 100Mbps service. The DS33Z41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS transmitted over the WAN interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the Ethernet port ...
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FEATURE HIGHLIGHTS 2.1 General • 169-pin, 14mm x 14mm CSBGA package • 1.8V supply with 3.3V tolerant inputs and outputs • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes ...
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SDRAM Interface • Interface for 128Mb, 32-bit-wide SDRAM • SDRAM Interface speed up to 100MHz • Auto Refresh Timing • Automatic Precharge • Master clock provided to the SDRAM • No external components required for SDRAM connectivity 2.7 MAC ...
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... Specifications compliance The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33Z41. Table 2-1. T1 Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications RFC1662—PPP in HDLC-like Framing RFC2615— ...
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... LAN Extension • Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design. Figure 3-1. Quad T1/E1 SCT to DS33Z41 HDLC/X.86 Serial Stream T1/E1 (IBO) ...
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ACRONYMS AND GLOSSARY • BERT—Bit Error Rate Tester • DCE—Data Communication Interface • DTE—Data Terminating Interface • FCS—Frame Check Sequence • HDLC—High Level Data Link Control • MAC—Media Access Control • MII—Media Independent Interface • RMII—Reduced Media Independent Interface ...
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... MAJOR OPERATING MODES Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor control is available in Section 8.1. 6 BLOCK DIAGRAMS Figure 6-1. Detailed Block Diagram ...
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... PHY are synchronous to this clock input for both transmit and receive. This required clock can 50MHz and should have ±100ppm accuracy. When in MII mode in DCE operation, the DS33Z41 uses this input to I generate the RX_CLK and TX_CLK outputs as required for the Ethernet PHY interface ...
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... Receive Data 0 through 3(MII). Four bits of received data, sampled synchronously with the rising edge of RX_CLK. For every clock cycle, the PHY transfers 4 bits to the DS33Z41. RXD[0] is the least significant bit of the data. Data is not considered valid when RX_DV is low. Receive Data 0 through 1(RMII). Two bits of received data, sampled synchronously with REF_CLK with 100Mbps mode ...
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... DCE Mode. MII Management data IO (MII). Data path for control information between the PHY and DS33Z41. When not used, pull to logic high externally through a 10kΩ resistor. The MDC and MDIO pins are used to write or read Control and Status Registers in 32 PHY Controllers ...
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... Reserved. Do not use Reserved. Do not use. DCE or DTE Selection. The user must set this pin high for DCE Mode selection or low for DTE Mode. In DCE Mode, the DS33Z41 MAC port can be directly connected to another MAC. In DCE Mode, the Transmit I clock (TX_CLK) and Receive clock (RX_CLK) are output by the DS33Z41 ...
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... SDRAM Bank Select. These 2 bits select banks for the read/write/precharge operations. I Note: All SDRAM operations are controlled entirely by the DS33Z41. No user programming for SDRAM buffering is required. SDRAM Row Address Strobe. Active-low output, used to latch the row address on rising edge of SDCLKO used with commands for Bank Activate, Precharge, and Mode Register Write ...
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... SYSCLKI. System Clock In. 100MHz System Clock input to the DS33Z41, used for internal operation. This clock is buffered and provided at SDCLKO I for the SDRAM interface. The DS33Z41 also provides a divided version output at the REF_CLKO pin. A clock supply with ±100ppm frequency accuracy is suggested. O SDRAM Chip Select ...
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NAME PIN TYPE G5–G10, H2, H5, VDD3.3 I H6, H7–H10 D3, D2, E3, F4, J4, K4, VDD1.8 L3, F10, I E11, E12, D12, M13, L12 A9, A12, B10, C10, D1, D5, E7, E8, F6, F8, F12, F13, VSS J5, J6, ...
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... Figure 7-1. DS33Z41 256-Ball CSBGA Pinout RMIIMIIS D VSS VDD1.8 VDD1.8 JTCLK VDD1.8 JTDI INT TCLKI TSER VDD1.8 G RSYNC RCLKI TSYNC SDMASK[1] H RSER VDD3 SDATA[10] SCAS J SDATA[11] SDATA[12] SDATA[8] VDD1.8 K SDATA[13] SDATA[14] VSS VDD1.8 L SDATA[15] SDATA[1] VDD1.8 SDATA[7] M SWE SDATA[0] SDATA[3] SDATA[9] ...
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... WAN. The WAN interface can be seamlessly connected to the Dallas Semiconductor/Maxim T1/E1/J1 Framers and Single-Chip Transceivers (SCTs). The DS33Z41 can be configured through an 8-bit Microprocessor interface port. The DS33Z41 also provides two on-board clock dividers for the System Clock input and Reference Clock Input for the 802.3 interfaces, further reducing the need for ancillary devices ...
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... Processor Interface Microprocessor control of the DS33Z41 is accomplished through the 20 interface pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins. When MODEC[1:0] = 00, bus timing is in Intel mode, as shown in MODEC[1:0] = 01, bus timing is in Motorola mode, as shown in space is mapped through the use of 8 address lines ...
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... Clock Structure The DS33Z41 clocks sources and functions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be gapped. • System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A clock supply with ± ...
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... Figure 8-1. Clocking for the DS33Z41 TSER HDLC TCLKI1 + Serial Line 1 IMUX Interface RCLKI1 RSER X.86 JTAG Microport CIR Arbiter SDRAM Interface SDCLKO SDRAM 25 of 167 Mhz Oscillator Buffer REF_CLK Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz TX_CLK1 RXD MAC RMII ...
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... While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and RX_CLK) are output by the DS33Z41, and are derived from the 25MHz REF_CLK input. More information on MII mode can be found in Section 8.14.1. ...
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... Serial interface Reset Queue Pointer Reset There are several features in the DS33Z41 to reduce power consumption. The reset bit in the minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization and configuration ...
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Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3. Clear all reset bits. Allow 5 milliseconds for the reset ...
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Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global ...
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Figure 8-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count ...
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... The DS33Z41 has a link aggregation feature that allows data from the Ethernet interface to be inverse multiplexed over bonded T1/E1 links. The T1/E1 data streams are input and output from the DS33Z41 on an 8.192Mbps Interleaved Bus (IBO). The IMUX function is shown graphically in ...
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Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 LIU Framer T1E1 T1E1 LIU Framer T1E1 LIU Framer T1E1 LIU Framer Figure 8-4. Diagram of Data Transmission with IMUX Operation Data on IBO Bus From TSER . . . 128 ...
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... HDLC/X.86 encoded data. The HDLC/X.86 encoding and decoding is data is only available when the DS33Z41 has performed an IMUX function. Hence on the line the FCS for a given HDLC packet could transport on a separate link than the HDLC data. ...
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IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Serial Interface is shown in The MSB for all commands is a “1”. The next 6 bits contain the actual opcode for ...
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The command and status registers for the IMUX function are detailed below: Table 8-4. Command and Status for the IMUX for Processor Communication REGISTER IMUX Configuration Register IMUX Command Register IMUX Sync Status Register IMUX Sync Latched Status Register IMUX ...
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Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monitoring is started. The device will declare an out of frame (OOF consecutive sequence errors are received. The device automatically adjusts for single-frame slips ...
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... The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the Ethernet and Serial interfaces. The DS33Z41 does not provide error indication if the user creates a connection and queue that overwrites data for another connection queue ...
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It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure ...
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... Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z41 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mechanisms that are used for flow control: • ...
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... The DS33Z41 will send a pause frame as the queue has crossed the high threshold and a frame is received. Pause is sent every time a frame is received in the “ ...
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Figure 8-6. Flow Control Using Pause Control Frame Receive Queue Growth 8.12.2 Half-Duplex Flow control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a ...
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... In MII operation, the interface contains 17 signals and a clock reference of 25MHz. The DS33Z41 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured for MII in DCE mode, REF_CLK must be 25MHz. The DS33Z41 will internally generate the TX_CLK and RX_CLK outputs (at 25MHz for 100Mbps, 2 ...
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... The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE connections for the DS33Z41 in MII mode are shown in the following two figures. ...
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... Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode Arbiter WAN DS33Z41 Rx RXD[3:0] RXD[3:0] DTE RXDV RXDV RX_CLK RX_CLK RX_ERR RX_ERR RX_CRS RX_CRS MAC COL_DET COL_DET TXD[3:0] TXD[3:0] TX_CLK Tx TX_CLK TX_EN TX_EN MDIO MDIO MDC MDC 44 of 167 Ethernet Phy ...
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... Figure 8-9. DS33Z41 Configured as a DCE in MII Mode WAN Arbiter DS33Z41 DCE Rx TXD[3:0] RXD[3:0] TX_EN RXDV RX_CLK TX_CLK RX_ERR TX_ERR RX_CRS RX_CRS MAC COL_DET COL_DET TXD[3:0] RXD[3:0] Tx TX_CLK RX_CLK TX_EN RXDV MDIO MDIO MDC MDC 45 of 167 DTE Tx MAC Rx ...
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... SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z41 when the operation is complete. Reading from the MAC registers requires the address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero to SU ...
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MII Mode The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section 8.2.2. ...
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... SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data Register. These indirect registers are accessed through the MAC Control Registers defined in The MDC clock is internally generated and runs at 1.67MHz. Note that the DS33Z41 provides a single MII Management port, and all control registers for this function are located in MAC 1. ...
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Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the ...
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Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Pattern Matches 8.15.4 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and counts the incoming bits. An OOS condition ...
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Performance Monitoring Update All counters stop counting at their maximum count. A counter register is updated by asserting (low to high transition) the performance monitoring update signal (PMU). During the counter register update process, the performance monitoring status signal ...
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Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The data output from the Transmit Packet Processor ...
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Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The ...
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FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet. If ...
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... Ethernet frames, but does not inflict dynamic bandwidth expansion as HDLC does. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33Z41 expects a byte synchronization signal to provide the byte boundary for the X.86 receiver. This is provided by the RSYNC pin ...
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... FCS for LAPS Flag(0x7E) MSB The DS33Z41 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X.86 mode in the register LI.TX86E. The DS33Z41 provides the following functions: • Control Registers for Address, SAPI, Destination Address, Source Address. ...
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The X86 received frame is aborted if: • detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets. • Control, SAPI and address ...
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... Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR can be used to restrict the transport of received MAC data to the serial port at a programmable rate. This is shown in from the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN ...
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Figure 8-16. CIR in the WAN Transmit Path TSER HDLC TCLKI1 + Serial Line 1 IMUX Interface RCLKI1 RSER X.86 JTAG Microport CIR Arbiter SDRAM Interface SDCLKO SDRAM 59 of 167 Mhz Oscillator Buffer Dev REF_CLKI Div ...
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... Table 9-1. Register Address Map Global Registers 0000h – 003Fh 0040h – 007Fh Port 1 - Reserved address space: 0180h - 07FFh. Table 9-1 Arbiter BERT 0080h – 00BFh - - 60 of 167 shows the register map for the DS33Z41. Serial Interface Ethernet Interface - - 00C0h – 013Fh 0140h – 017Fh ...
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... IMUXC6 IMUXC5 IMUXC4 ITSYNC3 ITSYNC2 ITSYNC1 IMUXDFD6 IMUXDFD5 IMUXDFD4 - - - - - - TOOFIE3 TOOFIE2 TOOFIE1 TOOFLS3 TOOFLS2 TOOFLS1 - - - - - - - - - - - - - - - SREFT6 SREFT5 SREFT4 61 of 167 contain the registers of the DS33Z41. Bits ID03 ID02 ID01 ID11 ID10 ID09 - REF_CLKO INTM - - - - - - - - REFCLKS - - - - - - - - - - - - - ...
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Arbiter Register Bit Map Table 9-3. Arbiter Register Bit Map DDR AME IT 040h AR.RQSC1 RQSC1[7] 041h AR.TQSC1 TQSC1[7] 9.1.3 BERT Register Bit Map Table 9-4. BERT Register Bit Map DDR ...
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Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map DDR AME IT 0C0h Reserved - 0C1h LI.RSTPD - 0C2h LI.LPBK - 0C3h Reserved - 0C4h LI.TPPCL - 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC ...
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DDR AME IT 103h LI.RMPSCH RMX15 104h LI.RPPSR - 105h LI.RPPSRL REPL 106h LI.RPPSRIE REPIE 107h Reserved 108h LI.RPCB0 RPC7 109h RPC15 LI.RPCB1 10Ah LI.RPCB2 RPC23 10Ch LI.RFPCB0 RFPC7 10Dh RFPC15 LI.RFPCB1 10Eh LI.RFPCB2 RFPC23 10Fh ...
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Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map DDR AME IT 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h MACRD23 145h SU.MACRD3 MACRD31 146h MACWD7 SU.MACWD0 ...
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MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map DDR AME IT SU.MACCR - 0000h 31:24 0001h 23:16 DRO 0002h 15:8 - 0003h 7:0 BOLMT1 BOLMT0 SU.MACAH - 0004h 31:24 0005h 23:16 - ...
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DDR AME IT 110h RESERVED – - initialize to FF 111h RESERVED – - initialize to FF RESERVED – 112h - initialize to FF 113h RESERVED – - initialize to FF 200h SU.RxFrmCtr RXFRMC31 RXFRMC30 RXFRMC29 ...
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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are preserved to provide code compatibility with the ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default Bit 2: REF_CLKO OFF (REF_CLKO). This bit determines the REF_CLKO output mode REF_CLKO is disabled and outputs an active-low signal REF_CLKO is ...
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Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity Latched Status Register Address: 04h Bit # 7 6 Name — — Default 0 0 Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1). This ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 4: Serial Interface 1 Tx Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS. Bit 0: Serial Interface 1 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit selects the Ethernet port that is to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — T1E1 Default 0 0 Bit 6: T1E1 Mode (T1E1). This bit determines if IMUX if for Mode Mode Mode ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name ITSYNC4 ITSYNC3 Default 0 0 Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the th ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name ITSYNCLS4 ITSYNCLS3 Default 0 0 Bit 7: IMUX Transmit Sync Latched Status 4 (ITSYNCLS4). This is a latched status bit for ITSYNC4. Bit 6: IMUX Transmit Sync Latched Status ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TOOFIE4 TOOFIE3 Default 0 0 Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4. Bit 6: IMUX Transmit OOF ...
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... Bit # 7 6 Name — — Default 0 0 Bit 1: BIST DONE (BISTDN). If this bit is set to 1, the DS33Z41 has completed the BIST Test initiated by BISTE. The pass fail result is available in BISTPF. GL.IMXOOFLS Inverse MUX Out Of Frame Latched Status 1Fh 5 4 TOOFLS2 TOOFLS1 ...
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... Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the SDRAM and the test passes. This bit is set the test failed. This bit is valid only after the BIST test is complete and the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z41. ...
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Register Name: Register Description Register Address: Bit # 7 6 Name SREFT7 SREFT6 Default 0 1 Bits SDRAM Refresh Time Control (SREFT7 to SREFT0). These 8 bits are used to control the SDRAM refresh frequency. The refresh ...
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... The queue address size is defined in increments of 32 packets. The range of bytes will depend on the external SDRAM connected to the DS33Z41. Transmit queue is the data queue for data arriving on the WAN that is sent to the MAC. Note that queue size not allowed and should never be set. ...
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BERT Registers Register Name: Register Description: Register Address: Bit # 7 6 Name — PMU Default 0 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU). This bit causes a ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — QRSS Default 0 0 The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with formula ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BSP7 BSP6 Default 0 0 Bits BERT Pattern (BSP7 to BPS0). Lower eight bits of 32 bits. Register description follows next register. Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bits Transmit Error Insertion Rate (TEIR2 to TEIR0). These three bits indicate the rate at which errors are inserted in the ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default — — Bit 3: Performance Monitor Update Status Latched (PMSL). This bit is set when the PMS bit transitions from Bit 2: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BEC7 BEC6 Default 0 0 Bits Bit Error Count (BEC7 to BEC0). Lower eight bits of 24 bits. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BC15 BC14 Default 0 0 Bits Bit Count (BC15 to BC8). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are ...
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Transmit HDLC Processor Registers Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Note: The user should take care not to modify this register value during packet error insertion. Bit 5: Transmit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TIFG7 TIFG6 Default 0 0 Bits Transmit Inter-Frame Gapping (TIFG7 to TIFG0). These eight bits indicate the number of additional flags and bytes of inter-frame fill ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS TPER6 Default 0 0 Bit 7: Manual Error Insert Mode Select (MEIMS). When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TPC7 TPC6 Default 0 0 Bits Transmit Packet Count (TPC7 to TPC0). Eight bits of 24-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TBC7 TBC6 Default 0 0 Bits Transmit Byte Count (TBC7 to TBC0). Eight bits of 32-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # 7 6 Name — — Default 0 0 Bit 0: Transmit PMU Update (TPMUU). This signal causes the transmit cell/packet processor block performance ...
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... Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86 headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is provided by the RSYNC signal and the DS33Z41 provides the transmit byte synchronization TSYNC. No HDLC encapsulation is performed. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TRSAPIL7 TRSAPIL6 Default 0 0 Bits X86 Transmit Receive Control (TRSAPIL7 to TRSAPIL0). This is the address field for the X.86 transmitter and expected value for ...
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Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMX15 RMX14 Default 0 0 Bits Receive Maximum Packet Size (RMX15 to RMX8). These 16 bits indicate the maximum allowable packet size in bytes. The size ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPL RAPL Default — — Bit 7: Receive FCS Errored Packet Latched (REPL). This bit is set when a packet with an errored FCS is detected. Bit 6: Receive ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPIE RAPIE Default 0 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE). This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RPC7 RPC6 Default 0 0 Bits Receive Packet Count (RPC7 to RPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RFPC7 RFPC6 Default 0 0 Bits Receive FCS Errored Packet Count (RFPC7 to RFPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RAPC7 RAPC6 Default 0 0 Bits Receive Aborted Packet Count (RAPC7 to RAPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RSPC7 RSPC6 Default 0 0 Bits Receive Size Violation Packet Count (RSPC7 to RSPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RBC7 RBC6 Default 0 0 Bits Receive Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REBC7 REBC6 Default 0 0 Bits Receive Aborted Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: ...
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Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7 6 Name — — Default 0 0 Bit 0: Receive PMU Update (RPMUU). This signal causes the receive cell/packet processor block performance ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: SAPI Octet Not Equal to LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet Not Equal to LI.RX86S.SAPILNE will generate an interrupt. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TQHT7 TQHT6 Default 0 0 Bits Transmit Queue High Threshold (TQHT7 to TQTH0). The transmit queue high threshold for the connection, in increments of 32 packets ...
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Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACRD15 MACRD14 Default 0 0 Bits MAC Read Data Byte 1 (MACRD15 to MACRD8). One of four bytes of data read from the MAC. Valid after ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACWD15 MACWD14 Default 0 0 Bits MAC Write Data Byte 1 (MACWD15 to MACWD08). One of four bytes of data to be written to the MAC. ...
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... SU.MACAWH and SU.MACAWL. Address information for read operations must be located in SU.MACRADL. The user must also write the MCS bit, and the DS33Z41 will clear MCS when the operation is complete. Bit 0: MAC Command Status (MCS). Setting MCS in conjunction with MCRW will initiate a read or write to the MAC registers ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: No Carrier Queue Flush Bar (NCFQ). If this bit is set to 1, the queue for data passing from Serial Interface to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name UR EC Default 0 0 Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FL7 FL6 Default 0 0 Bits Frame Length (FL7 to FL0). These 8 bits are the low byte of the length (in bytes) of the received ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MF — Default 0 0 Bit 7: Missed Frame (MF). This bit is set the packet is not successfully received from the MAC by the packet ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMPS7 RMPS6 Default 1 1 Bits Receiver Maximum Frame (RMPS7 to RMPS0). Eight bits of 16-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE). If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — UCFR Default 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR). When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal ...
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... MAC Registers The control registers related to the control of the individual MACs are shown in the following tables. The DS33Z41 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Note that the addresses listed are the indirect addresses that must be provided ...
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Bit 12: Late Collision Control (LCC). When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY). When set to ...
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Register Name: Register Description: Register Address: 0004h: Bit # 31 30 Name Reserved Reserved Default 1 1 0005h: Bit # 23 22 Name Reserved Reserved Default 1 1 0006h: Bit # 15 14 Name PADR47 PADR46 Default 1 1 0007h: ...
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... Bit 1: MII Write (MIIW). Write this bit order to execute a write instruction over the MDIO interface. Write the bit to zero to execute a read instruction. Bit 0: MII Busy (MIIB). This bit is set the DS33Z41 during execution of a MII management instruction through the MDIO interface, and is set to zero when the DS33Z41 has completed the instruction. The user should read this bit and ensure that it is equal to zero prior to beginning a MDIO instruction ...
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Register Name: Register Description: Register Address: 0018h: Bit # 31 30 Name Reserved Reserved Default 0 0 0019h: Bit # 23 22 Name Reserved Reserved Default 0 0 001Ah: Bit # 15 14 Name MIID15 MIID14 Default 0 0 001Bh: ...
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... Bit 0: Flow Control Busy (FCB) The host can set this bit order to initiate transmission of a pause frame. During transmission of a pause frame, this bit remains set. The DS33Z41 will clear this bit when transmission of the pause frame has been completed. The user should read this bit and ensure that this bit is equal to zero prior to initiating a pause frame ...
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Register Name: Register Description: Register Address: 0100h: Bit # 31 30 Name Reserved Reserved Default 0 0 0101h: Bit # 23 22 Name Reserved Reserved Default 0 0 0102h: Bit # 15 14 Name Reserved Reserved Default 0 0 0103h: ...
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Register Name: Register Description: Register Address: 010Ch: Bit # 31 30 Name Reserved Reserved Default 0 0 010Dh: Bit # 23 22 Name Reserved Reserved Default 0 0 010Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 010Fh: ...
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Register Name: Register Description: Register Address: 0110h: Bit # 31 30 Name Reserved Reserved Default 0 0 0111h: Bit # 23 22 Name Reserved Reserved Default 0 0 0112h: Bit # 15 14 Name Reserved Reserved Default 0 0 0113h: ...
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Register Name: Register Description: Register Address: 0200h: Bit # 31 30 Name RXFRMC31 RXFRMC30 Default 0 0 0201h: Bit # 23 22 Name RXFRMC23 RXFRMC22 Default 0 0 0202h: Bit # 15 14 Name RXFRMC15 RXFRMC14 Default 0 0 0203h: ...
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Register Name: Register Description: Register Address: 0204h: Bit # 31 30 Name RXFRMOK31 RXFRMOK30 Default 0 0 0205h: Bit # 23 22 Name RXFRMOK23 RXFRMOK22 Default 0 0 0206h: Bit # 15 14 Name RXFRMOK15 RXFRMOK14 Default 0 0 0207h: ...
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Register Name: Register Description: Register Address: 0300h: Bit # 31 30 Name TXFRMC31 TXFRMC30 Default 0 0 0301h: Bit # 23 22 Name TXFRMC23 TXFRMC22 Default 0 0 0302h: Bit # 15 14 Name TXFRMC15 TXFRMC14 Default 0 0 0303h: ...
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Register Name: Register Description: Register Address: 0308h: Bit # 31 30 Name TXBYTEC31 TXBYTEC30 Default 0 0 0309h: Bit # 23 22 Name TXBYTEC23 TXBYTEC22 Default 0 0 030Ah: Bit # 15 14 Name TXBYTEC15 TXBYTEC14 Default 0 0 030Bh: ...
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Register Name: Register Description: Register Address: 030Ch: Bit # 31 30 Name TXBYTEOK31 TXBYTEOK30 Default 0 0 030Dh: Bit # 23 22 Name TXBYTEOK23 TXBYTEOK22 Default 0 0 030Eh: Bit # 15 14 Name TXBYTEOK15 TXBYTEOK14 Default 0 0 030Fh: ...
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Register Name: Register Description: Register Address: 0334h: Bit # 31 30 Name TXFRMU31 TXFRMU30 Default 0 0 0335h: Bit # 23 22 Name TXFRMU23 TXFRMU22 Default 0 0 0336h: Bit # 15 14 Name TXFRMU15 TXFRMU14 Default 0 0 0337h: ...
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Register Name: Register Description: Register Address: 0338h: Bit # 31 30 Name TXFRMBD31 TXFRMBD30 Default 0 0 0339h: Bit # 23 22 Name TXFRMBD23 TXFRMBD22 Default 0 0 033Ah: Bit # 15 14 Name TXFRMBD15 TXFRMBD14 Default 0 0 033Bh: ...
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... In Half-Duplex (DTE) Mode, the DS33Z41 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the COL input, the DS33Z41 will replace the data nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the packet a maximum of 16 times ...
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Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first Nibble of the preamble in 100Mbps ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage (VDD3.3) Range with Respect to V Supply Voltage (VDD1.8) Range with Respect to V Ambient Operating Temperature Range………………………………………………...…………………–40ºC to +85ºC Junction Operating Temperature ...
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Note 1: Typical power is 145mW. All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to V Note 2: Note 3: RST pin held low, or RST bit set. Note 4: RST pin ...
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MII Interface Table 11-5. Transmit MII Interface PARAMETER SYMBOL TX_CLK Period TX_CLK Low Time TX_CLK High Time TX_CLK to TXD, TX_EN Delay Figure 11-1. Transmit MII Interface TX_CLK TXD[3:0] TX_EN 10Mbps MIN TYP t1 400 t2 140 t3 140 ...
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Table 11-6. Receive MII Interface PARAMETER SYMBOL RX_CLK Period RX_CLK Low Time RX_CLK High Time RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time Figure 11-2. Receive MII Interface Timing RX_CLK RXD[3:0] RX_DV 10Mbps MIN TYP MAX ...
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RMII Interface Table 11-7. Transmit RMII Interface PARAMETER SYMBOL REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time REF_CLK to TXD, TX_EN Delay Figure 11-3. Transmit RMII Interface REF_CLK TXD[1:0] TX_EN 10Mbps MIN TYP 50MHz ±50ppm t1 20 ...
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Table 11-8. Receive RMII Interface PARAMETER SYMBOL REF_CLK Frequence REF_CLK Period REF_CLK Low Time REF_CLK High Time RXD, CRS_DV to REF_CLK Setup Time REF_CLK to RXD, CRS_DV Hold Time Figure 11-4. Receive RMII Interface Timing REF_CLK RXD[1:0] CRS_DV 10Mbps MIN ...
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MDIO Interface Table 11-9. MDIO Interface PARAMETER MDC Frequency MDC Period MDC Low Time MDC High Time MDC to MDIO Output Delay MDIO Setup Time MDIO Hold Time Figure 11-5. MDIO Timing MDC MDIO MDC MDIO SYMBOL MIN t1 ...
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Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER TCLKI Frequency TCLKI Period TCLKI Low Time TCLKI High Time TCLKI to TSER Output Delay TSYNC Setup Time TSYNC Hold Time Figure 11-6. Transmit WAN Timing TCLKI TSER TSYNC SYMBOL ...
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Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER RCLKI Frequency RCLKI Period RCLKI Low Time RCLKI High Time RSER Setup Time RSYNC Setup Time RSER Hold Time RSYNC Hold Time Figure 11-7. Receive WAN Timing RCLKI RSER RSYNC ...
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SDRAM Timing Table 11-12. SDRAM Interface Timing PARAMETER SDCLKO Period SDCLKO Duty Cycle SDCLKO to SDATA Valid Write to SDRAM SDCLKO to SDATA Drive On Write to SDRAM SDCLKO to SDATA Invalid Write to SDRAM SDCLKO to SDATA Drive ...
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Figure 11-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) SDATA (input) SRAS, SCAS, SWE, SDCS (output) SDA, SBA (output) SDMASK (output t11 t13 152 of 167 t10 t12 t14 ...
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Figure 11-9. Receive IBO Channel Interleave Mode Timing RSYNC L3 C32 L4 C32 RSER RCLKI RSYNC LINK 4, CHANNEL 32 RSER Note 1: 8.192MHz bus configuration. Note 2: Data on unused channels must be filled with all ones. LINK #1, ...
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Figure 11-10. Transmit IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Unused channels filled with FFh. 154 of 167 ...
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Microprocessor Bus AC Characteristics Table 11-13. AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± PARAMETER Setup Time for A[12:0] Valid to CS Active Setup Time for CS Active to either RD Active ...
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Figure 11-11. Intel Bus Read Timing (MODEC = 00) Address Valid ADDR[12:0] DATA[7: Figure 11-12. Intel Bus Write Timing (MODEC = 00) Address Valid ADDR[12:0] DATA[7: Data Valid t5 ...
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Figure 11-13. Motorola Bus Read Timing (MODEC = 01) Address Valid ADDR[12:0] DATA[7: Figure 11-14. Motorola Bus Write Timing (MODEC = 01) Address Valid ADDR[12:0] DATA[7: Data Valid t5 ...
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JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5 -40°C to +85°C.) PARAMETER JTCLK Clock Period JTCLK Clock High:Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS ...
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JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan ...
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JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS ...
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Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in ...
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Figure 12-2. TAP Controller State Diagram Test Logic 1 Reset 0 1 Run Test/ 0 Idle 12.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When ...
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Table 12-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE 12.2.1 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be ...
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... Table 12-2. ID Code Structure REVISION DEVICE ID[31:28] DS33Z41 0000 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the device design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller ...
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JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 169-Ball CSBGA, 14mm x 14mm (56-G6035-001) ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DS33Z41 Quad IMUX Ethernet Mapper DESCRIPTION 167 of 167 ...