DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 112

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6 Ethernet Interface Registers
The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters
as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers
below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are
shown in
9.6.1 Ethernet Interface Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: MAC Read Address (MACRA7 to MACRA0). Low byte of the MAC address. Used only for read
operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: MAC Read Address (MACRA15 to MACRA8). High byte of the MAC address. Used only for read
operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: MAC Read Data Byte 0 (MACRD7 to MACRD0). One of four bytes of data read from the MAC. Valid
after a read command has been issued and the SU.MACRWC.MCS bit is zero.
Table
MACRA7
MACRD7
MACRA15
9-7. Accessing the MAC Registers is described in the Section 8.14.
7
0
7
0
7
0
MACRD6
MACRA6
MACRA14
6
0
0
6
0
6
SU.MACRADL
MAC Read Address Low Register
140h
SU.MACRADH
MAC Read Address High Register
141h
SU.MACRD0
MAC Read Data Byte 0
142h
MACRA5
MACRD5
MACRA13
5
0
5
0
5
0
MACRD4
MACRA4
MACRA12
112 of 167
4
0
4
0
4
0
MACRD3
MACRA3
MACRA11
3
0
3
0
3
0
MACRA2
MACRD2
MACRA10
2
0
2
0
2
0
MACRD1
MACRA1
MACRA9
1
0
1
0
1
0
MACRA0
MACRD0
MACRA8
0
0
0
0
0
0