DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 70

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1). This bit is set to 1 if the receive
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Bit 0: Transmit Serial Interface Clock Activity Latched Status 1 (TLCALS1). This bit is set to 1 if the transmit
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: Reference Clock Activity Latched Status (REFCLKS). This bit is set to 1 if REF_CLK has activity. This
bit is cleared upon read.
Bit 0: System Clock Input Latched Status (SYSCLS). This bit is set to 1 if SYSCLKI has activity. This bit is
cleared upon read.
—
—
7
0
7
0
—
—
6
0
6
0
GL.RTCAL
Global Receive and Transmit Serial Port Clock Activity Latched Status
04h
GL.SRCALS
Global SDRAM Reference Clock Activity Latched Status
05h
—
—
5
0
5
0
RLCALS1
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—
4
0
4
0
—
—
3
0
3
0
—
—
2
0
2
0
REFCLKS
—
1
0
1
0
TLCALS1
SYSCLS
0
0
0
0