DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 46

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.14 Ethernet MAC
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to
SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to
SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z41 when the operation is complete.
Reading from the MAC registers requires the
address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero to
SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33Z41 when the operation is complete. After MCS
is clear, valid data is available in SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated (read
or write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been cleared by
the device. The MAC Registers are detailed in the following table.
Table 8-8. MAC Control Registers
Table 8-9. MAC Status Registers
030Ch-030Fh
0308h-030Bh
0338h-033Bh
001Ch-001Fh
0200h-0203h
0204h-0207h
0300h-0303h
0334h-0337h
0008h-000Bh
0018h-001Bh
0000h-0003h
0004h-0007h
0014h-0017h
0100h-0103h
ADDRESS
ADDRESS
SU.TxBytesOkCtr Number of Bytes Transmitted with good frames
SU.TxBdFrmsCtr Transmit Number of Frames Aborted
SU.RxFrmOKCtr Number of Received Frames that are Good
SU.MMCCTRL
SU.TxFrmUndr
SU.TxBytesCtr
SU.RxFrmCntr
SU.MACMIIA
SU.MACMIID
SU.MACFCR
SU.TxFrmCtr
SU.MACCR
SU.MACAH
SU.MACAL
REGISTER
REGISTER
MAC Control Register. This register is used for programming full
duplex, half duplex, promiscuous mode, and back-off limit for half
duplex. The transmit and receive enable bits must be set for the
MAC to operate.
MAC Address High Register. This provides the physical address for
this MAC.
MAC Address Low Register. This provides the physical address for
this MAC.
MII Address Register. The address for PHY access through the
MDIO interface.
MII Data Register. Data to be written to (or read from) the PHY
through MDIO interface.
Flow Control Register
MMC Control Register bit 0 for resetting the status counters
All Frames Received counter
Number of Frames Transmitted
Number of Bytes Transmitted
Transmit FIFO underflow counter
SU.MACRADH
46 of 167
and
SU.MACRADL
DESCRIPTION
DESCRIPTION
registers to be written with the
SU.MACAWL
and