DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 8

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2.1 General
2.2 Link Aggregation (Inverse Multiplexing)
2.3 HDLC
2.4 Committed Information Rate (CIR) Controller
2.5 X.86 Support
FEATURE HIGHLIGHTS
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169-pin, 14mm x 14mm CSBGA package
1.8V supply with 3.3V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
Link aggregation for up to 4 T1/E1 Links
8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers
Differential delay compensation up to 7.75ms for the 4 T1/E1 links
Handshaking protocol between local and distant end for establishment of aggregation
HDLC controller engine
Compatible with polled or interrupt driven environments
Programmable FCS insertion and extraction
Programmable FCS type
Supports FCS error insertion
Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)
Supports bit stuffing/destuffing
Selectable packet scrambling/descrambling (X
Separate FCS errored packet and aborted packet counts
Programmable inter-frame fill for transmit HDLC
CIR controller limits transmission of data from the Ethernet Interface to the Serial Interface.
CIR granularity at 512kbps
CIR Averaging for smoothing traffic peaks
Programmable X.86 address/control fields for transmit and receive
Programmable 2-byte protocol (SAPI) field for transmit and receive
32 bit FCS
Transmit Transparency processing - 7E is replaced by 7D, 5E
Transmit Transparency processing – 7D replaced by 7D, 5D
Receive rate adaptation (7D, DD) is deleted.
Receive Transparency processing - 7D, 5E is replaced by 7E
Receive Transparency processing – 7D, 5D is replaced by 7D
Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect
Self-synchronizing X
Frame indication due to bad Address/Control/SAPI, FCS error, abort sequence or frame size longer
than preset max.
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+1 payload scrambling.
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