CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 93

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
be completely received. Usually, the DMA re-
ceive frame interrupt (RxDMAiE, bit 7, Regis-
ter B, BufCFG) is set so that the CS8900A
generates an interrupt when a frame is trans-
ferred by DMA. Figure 25 shows how a DMA
Receive Frame interrupt is processed.
In the interrupt service routine, the BufEvent
register (register C), bit RxDMA Frame (bit 7)
indicates that one or more receive frames
were transferred using DMA. The software
driver
PDMA_START) that will point to the beginning
of a new frame. After the CS8900A is initial-
ized and before any frame is received, pointer
PDMA_START points to the beginning of the
DMA buffer memory area. The first read of the
CS8900A
Crystal LAN™ Ethernet Controller
"Holes" due to
should
Base Address
double-word
DMA Buffer
alignment
maintain
a
Figure 24. Example of Frames Stored in DMA
CIRRUS LOGIC PRODUCT DATASHEET
pointer
RxStatus - Frame 1
(e.g.
RxLength - Frame 1
RxStatus - Frame 3
RxLength - Frame 3
RxStatus - Frame 2
RxLength - Frame 2
Frame 3
Frame 1
DMA Frame Count, CDMA, commits the mem-
ory covered by the CDMA count, and the DMA
cannot overwrite this committed space until
the space is freed. The driver then processes
the frames described by the CDMA count and
makes a second read of the DMA frame count.
This second read frees the buffer memory
space described by the CDMA counter.
During the frame processing, the software
should advance the PDMA_START pointer. At
the end of processing a frame, pointer
PDMA_START should be made to align with a
double-word boundary. The software remains
in the loop until the DMA frame count read is
zero.
Frame 2
register (PacketPage
DMA Start of Frame
base + 0126H)
points here.
(PacketPage base + 012Ah)
DMA Byte Count
93