CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 55
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CS8900A-IQ3ZR
Manufacturer Part Number
CS8900A-IQ3ZR
Description
Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8900A-CQZ.pdf
(138 pages)
Specifications of CS8900A-IQ3ZR
Ethernet Connection Type
10Base- 2, 10Base- 5, 10Base- F, 10Base- T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Maximum Operating Temperature
+ 85 C
Package / Case
LQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS8900A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS271F5
4.4.7 Register 4: Receiver Event
(RxEvent, Read-only, Address: PacketPage base + 0124h)
Alternate meaning if bits 8 and 9 are both set (see Section 5.2.10 on page 87 for exception regarding Broadcast
frames).
RxEvent reports the status of the current received frame.
000100
IAHash
Dribblebits
RxOK
Hashed
IndividualAdr
Broadcast
CRCerror
Runt
Extradata
Reset value is: 0000 0000 0000 0100
Notes: 3. All RxEvent bits are cleared upon readout. The host is responsible for processing all event bits.
CS8900A
Crystal LAN™ Ethernet Controller
Dribblebits
Dribblebits
7
F
7
F
4. RxStatus register (PacketPage base + 0400h) is the same as the RxEvent register except RxStatus is
not cleared when RxEvent is read. See Section 5.2 on page 78. The value in the RxEvent register is
undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set.
Extradata
IAHash
IAHash
Hash Table Index (see Section 5.2.10 on page 87)
will be 000100, where the LSB corresponds to Bit 0.
and only if IAHashA (Register 5, RxCTL, Bit 6) is set, and Hashed (Bit 9) is set. See
Section 5.2.10 on page 87.
ment Error" occurs when Dribblebits and CRCerror (Bit C) are both set.
error, or Extradata error). When RxOK is set, then the length of the received frame is contained
at PacketPage base + 0402h. If RxOKiE (Register 3, RxCFG, Bit 8) is set, there is an interrupt.
Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the Hash Table Index
for this frame [See Section 5.2.10 on page 87 for an exception regarding broadcast frames!].If
Hashed and RxOK are not both set, then Bits F through A are individual event bits as defined
below.
at PacketPage base + 0158h, then this bit is set if, and only if, RxOK (Bit 8) is set and Individ-
ualA (Register 5, RxCTL, Bit A) is set.
dress, then this bit is set if, and only if, RxOK is set and BroadcastA (Register 5, RxCTL, Bit B)
is set.
is an interrupt
there is an interrupt.
ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt.
These bits identify this as the Receiver Event Register. When reading this register, these bits
If the received frame's Destination Address is accepted by the hash filter, then this bit is set if,
If set, the received frame had from one to seven bits after the last received full byte. An "Align-
If set, the received frame had a good CRC and valid length (i.e., there is not a CRC error, Runt
If set, the received frame had a Destination Address that was accepted by the hash filter. If
If the received frame had a Destination Address which matched the Individual Address found
If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Destination Ad-
If set, the received frame had a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit C) is set, there
If set, the received frame was shorter than 64 bytes. If RuntiE (Register 3, RxCFG, Bit D) is set,
If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are discarded. If
E
E
6
6
Runt
D
D
5
5
CIRRUS LOGIC PRODUCT DATASHEET
CRCerror
C
C
4
4
Broadcast
B
B
3
3
000100
000100
Individual Adr
A
A
2
2
Hashed = 1
Hashed
1
9
1
9
RxOK = 1
RxOK
0
8
0
8
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