CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 90

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes: 6. Broadcast frames are accepted as Multicast frames if and only if all the following conditions are met
5.3 Receive DMA
5.3.1 Overview
The CS8900A supports a direct interface to
the host DMA controller allowing it to transfer
receive frames to host memory via slave DMA.
The DMA option applies only to receive
frames, and not transmit operation. The
CS8900A offers three possible Receive DMA
modes:
1) Receive-DMA-only
2) Auto-Switch DMA: DMA is used only when
3) StreamTransfer: DMA is used to minimize
This section provides a description of Receive-
DMA-only mode. Section 5.4 on page 94 de-
scribes Auto-Switch DMA and Section 5.5 on
page 96 describes StreamTransfer.
5.3.2 Configuring the CS8900A for DMA
Operation
The CS8900A interfaces to the host DMA con-
troller through one pair of the DMA request/ac-
Received
90
Address
Address
Type of
Frame
Broad-
cast
frames are transferred via DMA.
needed to help prevent missed frames.
the number of interrupts to the host.
7. NOT (Note 1).
Frame?
simultaneously:
a) the Logical Address Filter is programmed as: (MSB) 0000 8000 0000 0000h (LSB). Note that this
LAF value corresponds to a Multicast Addresses of both all 1s and 03-00-00-00-00-01.
b) the Rx Control Register (register 5) is programmed to accept IndividualA, MulticastA, RxOK-only,
and the following address filters were enabled: IAHashA and BroadcastA.
Erred
yes
no
no
no
don’t care ExtraData Runt CRC Error Broadcast Individual Adr
(Note 6)
(Note 7)
Passes
Filter?
Hash
yes
yes
no
mode:
Table 26. Contents of RxEvent Upon Various Conditions
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
CIRRUS LOGIC PRODUCT DATASHEET
All
receive
(actual value X00010)
Bits F-A
knowledge pins (see Section 3.2 on page 18
for a description of the CS8900A's DMA inter-
face).
Four 16-bit registers are used for DMA opera-
tion. These are described in Table 27.
Receive-DMA-only mode is enabled by setting
the RxDMAonly bit (Register 3, RxCFG, Bit 9).
Note: If the RxDMAonly bit and the AutoRxD-
MAE bit (Register 3, RxCFG, Bit A) are both
set, then RxDMAonly takes precedence, and
the CS8900A is in DMA mode for all receive
frames.
PacketPage
Address
0024h
0026h
Contents of RxEvent
Table 27. Receive DMA Registers
DMA Channel Number: DMA chan-
nel number (0, 1, or 2) that defines the
DMARQ/DMACK pin pair used.
DMA Start of Frame: 16-bit value that
defines the offset from the DMA base
address to the start of the most
recently transferred received frame.
Crystal LAN™ Ethernet Controller
Register Description
Hashed
Bit 9
1
0
0
0
RxOK
Bit 8
CS8900A
1
1
1
0
DS271F5
IAHash
Bit 6
0
0
0
0