CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 83

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
frame reported in
RxEvent register,
into on-chip RAM
Status of receive
frame accepted
Figure 21. Receive Frame Pre-Processing
Yes
Interrupts if Enabled
Generate Interrupts
Check:
- PromiscuousA?
- IAHashA?
- MulticastA?
- IndividualA?
- BroadcastA?
Acceptance Filter
Pre-Processing
(see next figure)
Receive Frame
Generate Early
Check:
- RxOKiE?
- ExtradataiE?
- CRCerroriE?
- RuntiE?
- RxDMAiE?
Address Filter
Check:
- RxOKA?
- ExtradataA?
- RuntA?
- CRCerrorA?
Destination
Complete
DA Filter?
Accept.
Filter?
Pass
Pass
Yes
No
No
CIRRUS LOGIC PRODUCT DATASHEET
frame reported in
RxEvent register,
Status of receive
frame discarded.
Discard Frame
Like all Event bits, RxDest and Rx128 are set
by the CS8900A whenever the appropriate
event occurs. Unlike other Event bits, RxDest
and Rx128 may be cleared by the CS8900A
without host intervention. All other event bits
are cleared only by the host reading the appro-
priate event register, either directly or through
the Interrupt Status Queue (ISQ). (RxDest and
Rx128 can also be cleared by the host reading
the BufEvent register, either directly or through
the Interrupt Status Queue). Figure 22 pro-
vides a diagram of the Early Interrupt process.
5.2.3.3 Acceptance Filtering
The third step of pre-processing is to deter-
mine whether or not to accept the frame by
comparing the frame with the criteria pro-
grammed into the RxCTL register (Register 5).
If the receive frame passes the Acceptance fil-
ter, the frame is buffered, either on chip or in
host memory via DMA. If the frame fails the
Acceptance filter, it is discarded. The results of
the Acceptance filter are reported in the Rx-
Event register (Register 4).
5.2.3.4 Normal Interrupt Generation
The final step of pre-processing is to generate
any enabled interrupts that are triggered by
the incoming frame. Interrupt generation oc-
curs when the entire frame has been buffered
(up to the first 1518 bytes). For more informa-
tion
Section 5.1 on page 78.
5.2.4 Held vs. DMAed Receive Frames
All accepted frames are either held in on-chip
RAM until processed by the host, or stored in
host memory via DMA. A receive frame that is
held in on-chip RAM is referred to as a held re-
ceive frame. A frame that is stored in host
memory via DMA is a DMAed receive frame.
tecting the incoming frame's End-of-Frame
(EOF) sequence.
about
interrupt
generation,
see
83