CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 100

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the LineCTL register (Register 13) and is de-
scribed in Table 31.
Note that the CS8900A transmits in 10BASE-
T mode when no link pulses are being re-
ceived only if bit DisableLT is set in register
Test Control (Register 19).
5.6.2.2 Selecting which Events Cause Inter-
rupts
The TxCFG register (Register 7) and the Buf-
CFG register (Register B) are used to deter-
mine which transmit events will cause
interrupts to the host processor. Tables 32 and
33 describe the interrupt enable (iE) bits in
these registers.
100
Bit
Bit
B
D
C
7
8
9
8
9
AutoAUI/10BT When set, automatic interface
Table 31. Physical Interface Configuration
Table 33. Transmit Interrupt Configuration
Bit Name
Bit Name
Rdy4TxiE
SerTxON
BackoffE
TxUnder
AUIonly
OvfloiE
DefDis
TxCol
2-part
runiE
Mod
Register 13, LineCTL
Register B, BufCFG
When set, transmission enabled.
When set, AUI selected (takes
precedence over AutoAUI/10BT).
When clear, 10BASE-T selected.
selection enabled.
When set, the modified backoff
algorithm is used. When clear,
the standard backoff algorithm is
used.
When set, two-part deferral is
disabled.
When set, there is an interrupt
whenever buffer space becomes
available for a transmit frame
(used with a Transmit Request).
When set, there is an interrupt
whenever the CS8900A runs out
of data after transmit has started.
When set, there is an interrupt
whenever the TxCol counter
overflows.
Operation
Operation
CIRRUS LOGIC PRODUCT DATASHEET
5.6.3 Changing the Configuration
When the host configures these registers it
does not need to change them for subsequent
packet transmissions. If the host does choose
to change the TxCFG or BufCFG registers, it
may do so at any time. The effects of the
change are noticed immediately. That is, any
changes in the Interrupt Enable (iE) bits may
affect the packet currently being transmitted.
If the host chooses to change bits in the
LineCTL register after initialization, the Mod-
BackoffE bit and any receive related bit (LoRx-
Squelch, SerRxON) may be changed at any
time. However, the Auto AUI/10BT and AUIon-
ly bits should not be changed while the SerTx-
ON bit is set. If any of these three bits are to be
changed, the host should first clear the SerTx-
ON bit (Register 13, LineCTL, Bit 7), and then
set it when the changes are complete.
Bit
A
B
F
6
7
8
9
Table 32. Transmitting Interrupt Configuration
SQErroriE
Bit Name
windowiE
AnycolliE
JabberiE
Loss-of-
TxOKiE
16colliE
Out-of-
CRSiE
Crystal LAN™ Ethernet Controller
Register 7, TxCFG
When set, there is an interrupt
whenever the CS8900A fails to
detect Carrier Sense after trans-
mitting the preamble (applies to
the AUI only).
When set, there is an interrupt
whenever there is an SQE error.
When set, there is an interrupt
whenever a frame is transmitted
successfully..
When set, there is an interrupt
whenever a late collision is
detected.
When set, there is an interrupt
whenever there is a jabber condi-
tion.
When set, there is an interrupt
whenever there is a collision.
When set, there is an interrupt
whenever the CS8900A attempts
to transmit a single frame 16
times.
Operation
CS8900A
DS271F5