EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 39

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Table 1–33. Memory Output Clock Jitter Specification for Stratix III Devices
© July 2010 Altera Corporation
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C2 speed grade is
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed
Number of DQS Delay
± 39 ps.
on a regional or global clock network as specified. Altera recommends using the regional clock networks whenever possible.
Table
Parameter
Table
Buffer
1
2
3
4
1–32:
1–33:
Table 1–31
Table 1–31. Average DQS Phase Offset Delay per Setting for Stratix III Devices
Table 1–32
(t
Table 1–33
Notes to
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear with a cumulative delay variation of ± 20 ps for all speed grades. For example, when
DQS_PSERR
Speed Grade
4 to 6.
using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected
minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.
C4L, I4L
C3, I3
C4, I4
Network
Regional
Regional
Regional
Global
Global
Global
C2
Clock
Table
) for Stratix III devices.
±13
±26
±39
±52
C2
lists the average DQS phase offset delay per setting for Stratix III devices.
lists the DQS phase shift error specification for DLL-delayed clock
lists the memory output jitter specification for Stratix III devices.
1–31:
tJIT(duty)
tJIT(duty) –120
tJIT(per)
tJIT(per)
tJIT(cc)
tJIT(cc)
Symbol
Min
7
7
7
7
–150
–113
–225
Min
–75
–80
V
CCL
C3, I3
C2
= 1.1V
±14
±28
±42
±56
Max
150
225
120
113
75
80
–170
–128
–255
–135
Min
–85
–90
V
11.5
11.5
CCL
Typ
10
11
C3, I3
DQS_PSERR
= 1.1V
(Note
Max
170
128
255
135
85
90
C4, C4L, I4, I4L
) for Stratix III Devices
1),
–100
–190
–100
–150
–285
–150
Min
V
±15
±30
±45
±60
(2)
CCL
C4, I4
= 1.1V
Max
Stratix III Device Handbook, Volume 2
Max
13
15
16
16
100
190
100
150
285
150
–100
–190
–100
–150
–285
–150
Min
V
CCL
(Note
= 1.1V
(Note 1)
Max
150
100
190
100
150
285
C4L, I4L
1), (2),
Unit
ps
ps
ps
ps
Unit
ps
ps
ps
ps
–120
–230
–140
–180
–340
–180
Min
V
CCL
(3)
1–29
= 0.9V
Max
120
230
140
180
340
180
Unit
ps
ps
ps
ps
ps
ps