EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 25

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Table 1–20. PLL Specifications for Stratix III Devices (Part 2 of 3)
f
t
t
t
t
t
t
CLBW
PLL_PSERR
ARESET
INCCJ
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
Symbol
(3),
(5),
(5)
(5)
(4)
(8)
PLL closed-loop low bandwidth
PLL closed-loop medium
bandwidth
PLL closed-loop high bandwidth
(6)
Accuracy of PLL phase shift
Minimum pulse width on areset
signal
Input clock cycle to cycle jitter
(F
Input clock cycle to cycle jitter
(F
Period Jitter for dedicated clock
output (F
Period Jitter for dedicated clock
output (F
Cycle to Cycle Jitter for dedicated
clock output
(F
Cycle to Cycle Jitter for dedicated
clock output
(F
Period Jitter for clock output on
regular IO (F
Period Jitter for clock output on
regular IO (F
REF
REF
OUT
OUT
 100 MHz)
< 100 MHz)
100 MHz)
< 100 MHz)
OUT
OUT
100 MHz)
< 100 MHz)
Parameter
OUT
OUT
 100 MHz)
< 100 MHz)
Min
—
—
—
—
10
—
—
—
—
—
—
—
—
V
CCL
Typ
= 1.1 V
0.3
1.5
C2
—
—
—
—
—
—
—
—
—
—
4
±750
Max
0.15
17.5
17.5
±50
175
175
600
—
—
—
—
60
Min
—
—
—
—
10
—
—
—
—
—
—
—
—
V
CCL
C3, I3
Typ
= 1.1 V
0.3
1.5
—
—
—
—
—
—
—
—
—
—
4
±750
0.15
17.5
17.5
Max
±50
175
175
600
—
—
—
—
60
Min
—
—
—
—
10
—
—
—
—
—
—
—
—
V
CCL
C4, I4
Typ
0.3
1.5
= 1.1 V
—
—
—
—
—
—
—
—
—
—
4
±750
Max
0.15
17.5
17.5
±50
175
175
600
—
—
—
—
60
Min
—
—
—
—
10
—
—
—
—
—
—
—
—
V
CCL
Typ
= 1.1 V
0.3
1.5
—
—
—
—
—
—
—
—
—
—
4
±750
Max
0.15
17.5
17.5
±50
175
175
600
—
—
—
—
60
C4L, I4L
Min
—
—
—
—
10
—
—
—
—
—
—
—
—
V
CCL
Typ
0.3
1.5
= 0.9 V
—
—
—
—
—
—
—
—
—
—
4
±500 ps (p-p)
Max
22.5
22.5
±50
225
225
750
0.1
—
—
—
—
75
UI (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
(p-p)
(p-p)
(p-p)
Unit
MHz
MHz
MHz
mUI
mUI
mUI
ps
ns