EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 293

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–131. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V
LVCMOS
2.5 V
1.8 V
1.5 V
1.2 V
Standard
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EP3SE260 I/O Timing Parameters
Table 1–131
EP3SE260 devices for single-ended I/O standards.
Table 1–131
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-1.242
-1.417
-1.242
-1.417
-1.253
-1.428
-1.253
-1.428
-1.248
-1.423
-1.270
-1.443
-1.260
-1.433
-1.208
-1.381
1.388
1.732
1.388
1.732
1.399
1.743
1.399
1.743
1.394
1.738
1.418
1.760
1.408
1.750
1.356
1.698
Fast Model
through
lists the EP3SE260 column pins input timing parameters for single-ended
Commercial
-1.186
-1.465
-1.186
-1.465
-1.197
-1.476
-1.197
-1.476
-1.192
-1.471
-1.214
-1.493
-1.204
-1.483
-1.152
-1.431
1.332
1.778
1.332
1.778
1.343
1.789
1.343
1.789
1.338
1.784
1.362
1.808
1.352
1.798
1.300
1.746
Table 1–135
-1.822 -1.915 -2.184 -2.050 -2.482 -1.915 -2.184 -2.050 -2.482
-2.238 -2.189 -2.558 -2.477 -3.038 -2.189 -2.558 -2.477 -3.038
-1.822 -1.915 -2.184 -2.050 -2.482 -1.915 -2.184 -2.050 -2.482
-2.238 -2.189 -2.558 -2.477 -3.038 -2.189 -2.558 -2.477 -3.038
-1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481
-2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037
-1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481
-2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037
-1.830 -1.929 -2.202 -2.068 -2.500 -1.929 -2.202 -2.068 -2.500
-2.246 -2.203 -2.576 -2.495 -3.056 -2.203 -2.576 -2.495 -3.056
-1.870 -1.965 -2.200 -2.066 -2.498 -1.965 -2.200 -2.066 -2.498
-2.286 -2.239 -2.574 -2.493 -3.054 -2.239 -2.574 -2.493 -3.054
-1.847 -1.933 -2.130 -1.996 -2.428 -1.933 -2.130 -1.996 -2.428
-2.263 -2.207 -2.504 -2.423 -2.984 -2.207 -2.504 -2.423 -2.984
-1.770 -1.834 -1.974 -1.840 -2.272 -1.834 -1.974 -1.840 -2.272
-2.186 -2.108 -2.348 -2.267 -2.828 -2.108 -2.348 -2.267 -2.828
2.045
2.727
2.045
2.727
2.044
2.726
2.044
2.726
2.053
2.735
2.093
2.775
2.070
2.752
1.993
2.675
1.1 V
V
C2
CCL
=
list the maximum I/O timing parameters for
2.146
2.697
2.146
2.697
2.148
2.699
2.148
2.699
2.160
2.711
2.196
2.747
2.164
2.715
2.065
2.616
1.1 V
V
C3
CCL
=
2.437
3.113
2.437
3.113
2.436
3.112
2.436
3.112
2.455
3.131
2.453
3.129
2.383
3.059
2.227
2.903
1.1 V
V
C4
CCL
=
2.285
3.000
2.285
3.000
2.284
2.999
2.284
2.999
2.303
3.018
2.301
3.016
2.231
2.946
2.075
2.790
1.1 V
V
CCL
=
C4L
2.724
3.584
2.724
3.584
2.723
3.583
2.723
3.583
2.742
3.602
2.740
3.600
2.670
3.530
2.514
3.374
0.9 V
V
CCL
Stratix III Device Handbook, Volume 2
=
2.146
2.697
2.146
2.697
2.148
2.699
2.148
2.699
2.160
2.711
2.196
2.747
2.164
2.715
2.065
2.616
1.1 V
V
CCL
I3
=
2.437
3.113
2.437
3.113
2.436
3.112
2.436
3.112
2.455
3.131
2.453
3.129
2.383
3.059
2.227
2.903
1.1 V
V
CCL
I4
=
2.285
3.000
2.285
3.000
2.284
2.999
2.284
2.999
2.303
3.018
2.301
3.016
2.231
2.946
2.075
2.790
1.1 V
V
CCL
1–283
=
I4L
2.724
3.584
2.724
3.584
2.723
3.583
2.723
3.583
2.742
3.602
2.740
3.600
2.670
3.530
2.514
3.374
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns