EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 37

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side
© July 2010 Altera Corporation
DDR3 SDRAM (with
Deskew circuitry,
401 MHz–533 MHz)
DDR3 SDRAM (8-tap
phase offset,
375 MHz–400 MHz)
DDR3 SDRAM (8-tap
phase offset,
360 MHz–375 MHz)
DDR3 SDRAM (10-tap
phase offset,
333 MHz–360 MHz)
DDR3 SDRAM (10-tap
phase offset,
300 MHz–333 MHz)
DDR3 SDRAM
(Non-leveling interface)
DDR2 SDRAM Differential
DQS
DDR2 SDRAM
Single-ended DQS
DDR SDRAM
Single-ended DQS
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation
Memory Type
(2)
Standard
1.5-V
1.5-V
1.5-V
1.5-V
1.5-V
1.5-V
1.8-V
1.8-V
2.5-V
1.5-V
HSTL
1.5-V
HSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
I/O
×9, ×18,
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
Width
×36
×36
Lead
253
293
293
169
169
268
229
316
313
290
310
V
TCCS (ps)
CCL
= 1.1 V
C2
Lag
262
284
284
470
470
246
246
168
157
278
298
Lead
341
341
217
217
230
230
318
315
292
312
V
—
(Note 1)
TCCS (ps)
CCL
C3, I3
= 1.1 V
332
373
496
496
355
355
239
222
388
408
Lag
—
(Part 1 of 2)
Lead
258
258
250
250
346
343
315
335
V
—
—
—
TCCS (ps)
CCL
C4, I4
Stratix III Device Handbook, Volume 2
= 1.1 V
Lag
528
528
388
388
260
242
421
441
—
—
—
Lead
258
258
250
250
346
343
315
335
V
—
—
—
TCCS (ps)
CCL
C4L, I4L
= 1.1 V
Lag
528
528
388
388
260
242
421
441
—
—
—
1–27
Lead
250
350
446
443
415
435
V
—
—
—
—
—
TCCS (ps)
CCL
C4L, I4L
= 0.9 V
388
488
360
342
521
541
Lag
—
—
—
—
—