EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 35

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Figure 1–3. LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for Stratix III Devices
© July 2010 Altera Corporation
f
Figure 1–3
for Stratix III devices.
Table 1–27
devices.
Table 1–27. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Stratix III Devices
External Memory Interface Specifications
The following sections describe the external memory I/O timing specifications and
the DLL and DQS block specifications.
For more information about the maximum clock rate support for external memory
interfaces with a half-rate or full-rate controller, refer to
Specifications
External Memory I/O Timing Specifications
Table 1–28
write data paths. Use these specifications to determine timing margins for source
synchronous paths between the Stratix III FPGA and the external memory device. For
more information, refer to the figure for “SW (sampling window)” in the
on page
F1
F2
F3
F4
1–326.
shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications
lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for Stratix III
and
Jitter Frequency (Hz)
of the External Memory Interfaces Handbook.
Table 1–29
50,000,000
1,493,000
list Stratix III device timing uncertainties on the read and
10,000
17,565
Jitter Amplitude
25.000
25.000
0.350
0.350
Section III: System Performance
Stratix III Device Handbook, Volume 2
“Glossary”
Unit
UI
UI
UI
UI
1–25