EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 134

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

1–124
Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part 3 of 3)
Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 7)
Stratix III Device Handbook, Volume 2
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
4mA
8mA
12mA
16mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
Table 1–73
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
Industrial
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
-0.830
-0.831
-0.830
-0.831
-0.931
-0.731
-0.931
-0.731
0.946
1.083
0.946
1.083
1.046
0.982
1.046
0.982
Industrial
Fast Model
lists the EP3SL150 column pins output timing parameters for single-ended
3.422
3.898
3.355
3.781
3.269
3.692
3.262
3.685
Fast Model
Commercial
-0.877
-0.821
-0.877
-0.821
-0.975
-0.730
-0.975
-0.730
1.008
1.089
1.008
1.089
1.105
0.998
1.105
0.998
Commercial
3.439
3.841
3.372
3.774
3.286
3.688
3.279
3.681
-1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655
-1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611
-1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655
-1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
1.426
1.754
1.426
1.754
1.541
1.645
1.541
1.645
1.1 V
V
C2
CCL
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
=
4.768
5.355
4.659
5.246
4.555
5.142
4.538
5.125
1.1 V
V
C2
CCL
=
1.556
1.986
1.556
1.986
1.678
1.857
1.678
1.857
1.1 V
V
C3
CCL
5.127
5.880
5.016
5.718
4.918
5.583
4.890
5.555
=
1.1 V
V
C3
CCL
=
1.558
2.221
1.558
2.221
1.913
1.968
1.913
1.968
1.1 V
V
C4
CCL
5.625 5.473
6.341 6.161
5.512 5.360
6.228 6.048
5.420 5.268
6.136 5.956
5.379 5.227
6.095 5.915
1.1 V
=
V
C4
CCL
=
1.612
2.102
1.612
2.102
1.854
1.852
1.854
1.852
1.1 V
V
CCL
1.1 V
V
=
CCL
C4L
=
C4L
1.831
2.045
1.831
2.045
2.176
1.793
2.176
1.793
0.9 V
V
CCL
5.808 5.127 5.625 5.473 5.808
6.543 5.880 6.341 6.161 6.543
5.695 5.016 5.512 5.360 5.695
6.430 5.718 6.228 6.048 6.430
5.603 4.918 5.420 5.268 5.603
6.338 5.583 6.136 5.956 6.338
5.562 4.890 5.379 5.227 5.562
6.297 5.555 6.095 5.915 6.297
0.9 V
V
=
CCL
© July 2010 Altera Corporation
=
1.558
2.003
1.558
2.003
1.697
1.866
1.697
1.866
1.1 V
V
CCL
I3
1.1 V
V
I3
CCL
=
=
1.566
2.237
1.566
2.237
1.922
1.988
1.922
1.988
1.1 V
V
1.1 V
V
I4
CCL
I4
CCL
=
=
I/O Timing
1.627
2.115
1.627
2.115
1.865
1.870
1.865
1.870
1.1 V
V
1.1 V
V
CCL
CCL
=
=
I4L
I4L
1.875
2.092
1.875
2.092
2.217
1.843
2.217
1.843
0.9 V
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns