EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 76

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

5–12
Clock Feedback Modes
Source-Synchronous Mode
Cyclone III Device Handbook, Volume 1
1
Cyclone III device family PLLs support up to four different clock feedback modes.
Each mode allows clock multiplication and division, phase shifting, and
programmable duty cycle.
Input and output delays are fully compensated by the PLL only when you are using
the dedicated clock input pins associated with a given PLL as the clock sources. For
example, when using PLL1 in normal mode, the clock delays from the input pin to the
PLL and the PLL clock output-to-destination register are fully compensated, provided
that the clock input pin is one of the following four pins:
■
■
■
■
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–8
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–8. Phase Relationship Between Data and Clock in Source-Synchronous Mode
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
■
■
CLK0
CLK1
CLK2
CLK3
Data pin to I/O element register input
Clock input pin to the PLL phase-frequency detector (PFD) input
shows an example waveform of the data and clock in this mode. Use this
clock at input pin
Clock at register
Data at register
PLL reference
Data pin
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
© December 2009 Altera Corporation
Clock Feedback Modes