EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 50

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

3–14
Figure 3–13. Cyclone III Device Family Shift Register Mode Configuration
ROM Mode
FIFO Buffer Mode
Cyclone III Device Handbook, Volume 1
f
w × m × n Shift Register
W
W
W
W
Figure 3–13
register mode.
Cyclone III device family M9K memory blocks support ROM mode. A .mif initializes
the ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
Cyclone III device family M9K memory blocks support single-clock or dual-clock
FIFO buffers. Dual clock FIFO buffers are useful when transferring data from one
clock domain to another clock domain. Cyclone III device family M9K memory blocks
do not support simultaneous read and write from an empty FIFO buffer.
For more information about FIFO buffers, refer to the
Megafunction User
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the Cyclone III device family M9K memory block in the shift
Guide.
Chapter 3: Memory Blocks in the Cyclone III Device Family
W
W
W
W
Single- and Dual-Clock FIFO
© December 2009 Altera Corporation
n Number of Taps
Memory Modes