EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 44

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

3–8
Memory Modes
Single-Port Mode
Cyclone III Device Handbook, Volume 1
f
1
1
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard
For more information, refer to the
There are three ways to reset registers in the M9K blocks:
■
■
■
Cyclone III device family M9K memory blocks allow you to implement
fully-synchronous SRAM memory in multiple modes of operation. Cyclone III device
family M9K memory blocks do not support asynchronous (unregistered) memory
inputs.
M9K memory blocks support the following modes:
■
■
■
■
■
■
Violating the setup or hold time on the M9K memory block input registers may
corrupt memory contents. This applies to both read and write operations.
Single-port mode supports non-simultaneous read and write operations from a single
address.
device family M9K memory blocks.
Figure 3–7. Single-Port Memory
Notes to
(1) You can implement two single-port memory blocks in a single M9K block.
(2) For more information, refer to
Power up the device
Use the aclr signal for output register only
Assert the device-wide reset signal using the DEV_CLRn option
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
Figure
Figure 3–7
3–7:
shows the single-port memory configuration for Cyclone III
“Packed Mode Support” on page
data[ ]
address[ ]
wren
byteena[]
addressstall
inclocken
rden
aclr
inclock
(Note
™
Plug-In Manager.
RAM Megafunction User
1),
(2)
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–5.
outclocken
outclock
q[]
© December 2009 Altera Corporation
Guide.
Memory Modes