EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 39

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Control Signals
Figure 3–1. M9K Control Signal Selection
Parity Bit Support
© December 2009
Local
Interconnect
Dedicated
Row LAB
Clocks
Altera Corporation
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
operations.
The rden and wren control signals control the read and write operations for each
port of M9K memory blocks. You can disable the rden or wren signals independently
to save power whenever the operation is not required.
Figure 3–1
the Cyclone III device family M9K memory block.
Parity checking for error detection is possible with the parity bit along with internal
logic resources. The Cyclone III device family M9K memory blocks support a parity
bit for each storage byte. You can use this bit as either a parity bit or as an additional
data bit. No parity function is actually performed on this bit.
6
clock_a
shows how the register clock, clear, and control signals are implemented in
clock_b
clocken_a
clocken_b
rden_a
rden_b
wren_a
wren_b
aclr_a
Cyclone III Device Handbook, Volume 1
aclr_b
addressstall_a
addressstall_b
byteena_a
byteena_b
3–3