EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 138

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

7–14
Figure 7–11. Differential SSTL Class II Interface
Note to
(1) PLL output clock pins do not support differential SSTL-18 Class II I/O standard.
Differential HSTL I/O Standard Support in the Cyclone III Device Family
Figure 7–12. Differential HSTL Class I Interface
Cyclone III Device Handbook, Volume 1
Figure
Output Buffer (1)
7–11:
f
Output Buffer
Figure 7–11
The differential HSTL I/O standard is used for the applications designed to operate in
0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic switching range. The Cyclone III
device family supports differential HSTL-18, HSTL-15, and HSTL-12 I/O standards.
The differential HSTL input standard is available on GCLK pins only, treating the
differential inputs as two single-ended HSTL and only decoding one of them. The
differential HSTL output standard is only supported at the PLL#_CLKOUT pins using
two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with
the second output programmed to have opposite polarity. The standard requires two
differential inputs with an external reference voltage (VREF), as well as an external
termination voltage (VTT) of 0.5 × V
For more information about the differential HSTL signaling characteristics, refer to the
Cyclone III Device I/O
Data Sheet
Figure 7–12
chapters.
shows the differential SSTL Class II interface.
shows the differential HSTL Class I interface.
V
TT
Features,
Z 0 = 50 Ω
Z 0 = 50 Ω
V
TT
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Cyclone III Device Data
V
TT
CCIO
50 Ω
to which termination resistors are connected.
V
TT
V
TT
50 Ω
Sheet, and
V
TT
© December 2009 Altera Corporation
Receiver
High-Speed I/O Standards Support
Cyclone III LS Device
Receiver