EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 102

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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6–2
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration
I/O Element Features
Programmable Current Strength
Cyclone III Device Handbook, Volume 1
Interconnect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Figure 6–1
The Cyclone III device family IOE offers a range of programmable features for an I/O
pin. These features increase the flexibility of I/O utilization and provide an
alternative to reduce the usage of external discrete components to on-chip, such as a
pull-up resistor and a diode.
The output buffer for each Cyclone III device family I/O pin has a programmable
current strength control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I
and II, HSTL-15 Class I and II, and HSTL-12 Class I and II I/O standards have several
levels of current strength that you can control.
Chip-Wide Reset
shows the Cyclone III device family IOE structure.
OE
clkout
oe_out
aclr/prn
clkin
oe_in
preset
sclr/
Output Register
OE Register
ENA
ENA
D
D
ACLR
/PRN
ACLR
/PRN
Q
Q
Input Register
ENA
D
ACLR
/PRN
Current Strength Control
Q
Slew Rate Control
Open-Drain Out
Chapter 6: I/O Features in the Cyclone III Device Family
Pin Delay
Output
Input Register
or Input Pin to
Logic Array
Input Pin to
Delay
Delay
V
CCIO
© December 2009 Altera Corporation
V
CCIO
Programmable
I/O Element Features
Resistor
Pull-Up
Bus Hold

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