EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 54

• Manufacturer Part Number: EP1S30F1020C5N
• Description: Stratix
• Manufacturer: Altera

Specifications of EP1S30F1020C5N

• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

TriMatrix Memory
Figure 2–21. Left-Facing M-RAM to Interconnect Interface
Notes to
(1)
(2)
2–40
Stratix Device Handbook, Volume 1
Only R24 and C16 interconnects cross the M-RAM block boundaries.
The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6
orientation is clipped across the vertical axis for right-facing M-RAM blocks.
Figure
LABs in Row
M-RAM Boundary
Row Unit Interface
Allows LAB Rows to
Drive Address and
Control Signals to
M-RAM Block
2–21:
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
LAB Interface
Blocks
M512 RAM Block Columns
B1
A1
B2
A2
M-RAM Block
B3
A3
Port B
Port A
Notes
B4
A4
(1),
(2)
B5
A5
B6
A6
Column Interface Block
Allows LAB Columns to
Drive datain and dataout to
and from M-RAM Block
Altera Corporation
LABs in Column
M-RAM Boundary
Column Interface Block
Drives to and from
C4 and C8 Interconnects
July 2005