EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 205

• Manufacturer Part Number: EP1S30F1020C5N
• Description: Stratix
• Manufacturer: Altera

Specifications of EP1S30F1020C5N

• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
January 2006
Table 4–54
clock networks.
Notes to
(1)
(2)
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
XZPLL
ZXPLL
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2
of 2)
Table 4–54. Stratix Global Clock External I/O Timing Parameters
(2)
Symbol
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
Table
Table
shows the external I/O timing parameters when using global
Setup time for input or bidirectional pin using IOE input register with
global clock fed by
Hold time for input or bidirectional pin using IOE input register with
global clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
(1),
4–53:
4–54:
(2)
CLK
CLK
pin
pin
Parameter
Parameter
Stratix Device Handbook, Volume 1
CLK
DC & Switching Characteristics
pin
Notes
(1),
4–35