EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 124

• Manufacturer Part Number: EP1S30F1020C5N
• Description: Stratix
• Manufacturer: Altera

Specifications of EP1S30F1020C5N

• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

I/O Structure
Figure 2–64. Stratix IOE in Bidirectional I/O Configuration
Note to
(1)
2–110
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
I/O Interconnect
Figure
[15..0]
2–64:
ioe_clk[7..0]
OE
clkout
ce_out
aclr/prn
clkin
ce_in
sclr/preset
The Stratix device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
Chip-Wide Reset
Register Delay
Logic Array
Enable Clock
Enable Delay
Enable Delay
Output Clock
to Output
Output
Enable Delay
Input Clock
Output Register
Input Register
OE Register
D
ENA
CLRN/PRN
ENA
D
ENA
CLRN/PRN
D
CLRN/PRN
Note (1)
Q
Q
Q
Drive Strength Control
Pin Delay
Output
Open-Drain Output
Input Register Delay
Logic Array Delay
Slew Control
Input Pin to
Input Pin to
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
Optional
PCI Clamp
V
CCIO
Bus-Hold
Circuit
July 2005
Programmable
Pull-Up
Resistor