EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 229

• Manufacturer Part Number: EP1S30F1020C5N
• Description: Stratix
• Manufacturer: Altera

Specifications of EP1S30F1020C5N

• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
January 2006
Table 4–98
clock to feed IOE registers in I/O banks around each device. These values
can be used for calculating the timing budget on the output (write) side
of a memory interface. These values already factor in the package skew.
Notes to
(1)
(2)
Note to
(1)
t
t
t
t
t
t
t
t
t
t
LR_HIO
TB_VIO
OVERALL
SB_HIO
SB_VIO
SS_HIO
SS_VIO
LR_HIO
TB_VIO
OVERALL
Table 4–97. Output Pin Timing Skew Definitions (Part 2 of 2)
Table 4–98. Output Skew for Stratix by Device Density
See
See
The skew numbers in
Symbol
Symbol
Table
Figure 4–5 on page
Figure 4–6 on page
Table
shows the I/O skews when using the same global or regional
4–98:
4–97:
EP1S10 to EP1S30
Across all HIO banks (1, 2, 5, 6); across four similar
type I/O banks
Across all VIO banks (3, 4, 7, 8); across four similar
type I/O banks
Output timing skew for all I/O pins on the device.
Table 4–98
4–57.
4–58.
160
180
150
190
430
90
90
account for worst case package skews.
Stratix Device Handbook, Volume 1
Skew (ps)
EP1S40
DC & Switching Characteristics
290
290
460
520
490
580
630
Definition
(1)
EP1S60 & EP1S80
500
500
600
630
600
670
880
4–59