EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 116

• Manufacturer Part Number: EP1S30F1020C5N
• Description: Stratix
• Manufacturer: Altera

Specifications of EP1S30F1020C5N

• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

PLLs & Clock Networks
2–102
Stratix Device Handbook, Volume 1
External Clock Inputs
Each fast PLL supports single-ended or differential inputs for source
synchronous transmitters or for general-purpose use. Source-
synchronous receivers support differential clock inputs. The fast PLL
inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK
pins, as shown in
Table 2–22
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
Table 2–22. Fast PLL Port I/O Standards (Part 1 of 2)
shows the I/O standards supported by fast PLL input pins.
I/O Standard
Figure 2–50 on page
2–85.
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Input
Altera Corporation
PLLENABLE
v
v
July 2005