ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 86

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Bit
5:4
3:2
1:0
IRQCLRE Register
Name:
Address:
Default value:
Access:
Value
11
10
01
00
11
10
01
00
11
10
01
00
IRQCLRE
0xFFFF0038
0x00000000
Read and write
Name
IRQ2SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
External IRQ2 triggers on falling edge.
External IRQ1 triggers on falling edge.
External IRQ0 triggers on falling edge.
Description
External IRQ2 triggers on rising edge.
External IRQ2 triggers on low level.
External IRQ2 triggers on high level.
External IRQ1 triggers on rising edge.
External IRQ1 triggers on low level.
External IRQ1 triggers on high level.
External IRQ0 triggers on rising edge.
External IRQ0 triggers on low level.
External IRQ0 triggers on high level.
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Table 120. IRQCLRE MMR Bit Designations
Bit
31:25
24
24
23
22
21
20
19
18:0
Name
Reserved
IRQ5CLRI
IRQ4CLRI
Reserved
IRQ3CLRI
IRQ2CLRI
IRQ1CLRI
IRQ0CLRI
Reserved
Description
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the IRQ5
interrupt service routine to clear an edge
triggered IRQ5 interrupt.
A 1 must be written to this bit in the IRQ4
interrupt service routine to clear an edge
triggered IRQ4 interrupt.
This bit is reserved.
A 1 must be written to this bit in the IRQ3
interrupt service routine to clear an edge
triggered IRQ3 interrupt.
A 1 must be written to this bit in the IRQ2
interrupt service routine to clear an edge
triggered IRQ2 interrupt.
A 1 must be written to this bit in the IRQ1
interrupt service routine to clear an edge
triggered IRQ1 interrupt.
A 1 must be written to this bit in the IRQO
interrupt service routine to clear an edge
triggered IRQ0 interrupt.
These bits are reserved and should not be
written to.