ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 40

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Reset Operation
There are four types of reset: external reset, power-on reset,
watchdog expiration, and software force. The RSTSTA register
indicates the source of the last reset and RSTCLR clears the
RSTSTA register. These registers can be used during a reset
Table 47. Remap MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00)
Bit
0
Table 48. RSTSTA MMR Bit Designations (Address = 0xFFFF0230, Default Value = 0x0X)
Bit
7:3
2
1
0
Name
Remap
Description
Reserved.
Software reset.
Set by the user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog timeout.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Set by the user to remap the SRAM to Address 0x00000000.
Description
Remap bit.
Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000.
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exception service routine to identify the source of the reset.
If RSTSTA is null, the reset was external. Note that when
clearing RSTSTA, all bits that are currently set to 1 must be
cleared. Otherwise, a reset event occurs.