ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
UART Interrupt Enable Register 0
This 8-bit register enables and disables the individual UART
interrupt sources.
Name:
Address:
Default value:
Access:
Table 84. COMIEN0 MMR Bit Designations
Bit
7 to 3
2
1
0
UART Interrupt Identification Register 0
This 8-bit register reflects the source of the UART interrupt.
Name:
Address:
Default value:
Access:
Name
ELSI
ETBEI
ERBFI
COMIEN0
0xFFFF0804
0x00
Read and write
COMIID0
0xFFFF0808
0x01
Read only
Description
Reserved. Not used.
Cleared by the user.
Receive pin (SIN) status interrupt enable
bit.
Set by the user to enable generation of
an interrupt if any of the COMSTA0[3:1]
register bits are set.
Cleared by the user.
Enable transmit buffer empty interrupt.
Set by the user to enable an interrupt
when the buffer is empty during a
transmission, that is, when COMSTA[5]
is set.
Cleared by the user.
Enable receive buffer full interrupt.
Set by the user to enable an interrupt
when the buffer is full during a
reception.
Cleared by the user.
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Table 85. COMIID0 MMR Bit Designations
Bits[2:1]
Status
Bits
00
11
10
01
00
UART Fractional Divider Register
This 16-bit register controls the operation of the fractional
divider for the ADuC7121.
Name:
Address:
Default value:
Access:
Table 86. COMDIV2 MMR Bit Designations
Bit
15
14:13
12:11
10:0
Name
FBEN
FBM[1:0]
FBN[10:0]
Bit 0
NINT
1
0
0
0
0
COMDIV2
0xFFFF082C
0x0000
Read and write
Description
Fractional baud rate generator enable bit.
Set by the user to enable the fractional
baud rate generator.
Cleared by the user to generate the baud
rate using the standard 450 UART baud rate
generator.
Reserved.
M. If FBM = 0, M = 4. See Equation 2 for the
calculation of the baud rate using a
fractional divider and Table 80 for common
baud rate values.
N. See Equation 2 for the calculation of the
baud rate using a fractional divider and
Table 80 for common baud rate values.
Priority
1
2
3
4
No interrupt
Receive line
status
interrupt
Receive
buffer full
interrupt
Transmit
buffer empty
interrupt
Modem
status
interrupt
Definition
Clearing
Operation
Read
COMSTA0
Read COMRX
Write data to
COMTX or
read COMIID0
Read
COMSTA1
register