ADSP-BF527KBCZ-6 Analog Devices Inc, ADSP-BF527KBCZ-6 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF527KBCZ-6
• Description: ADSP-BF527 Processor,600Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. System Interrupt Controller (SIC) (Continued)
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
Peripheral Interrupt Event
OTP Memory Interrupt
GP Counter
DMA Channel 1 (MAC RX/HOSTDP)
Port H Interrupt A
DMA Channel 2 (MAC TX/NFC)
Port H Interrupt B
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port G Interrupt A
Port G Interrupt B
MDMA Stream 0
MDMA Stream 1
Software Watchdog Timer
Port F Interrupt A
Port F Interrupt B
SPI Status
NFC Status
HOSTDP Status
Host Read Done
USB_EINT Interrupt
USB_INT0 Interrupt
USB_INT1 Interrupt
USB_INT2 Interrupt
USB_DMAINT Interrupt
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
• CEC interrupt latch register (ILAT) — Indicates when
• CEC interrupt mask register (IMASK) — Controls the
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
General Purpose
Interrupt (at RESET) Peripheral Interrupt ID
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG13
IVG13
IVG13
IVG13
IVG13
IVG7
IVG7
IVG7
IVG7
IVG10
IVG10
IVG10
IVG10
IVG10
Rev. B | Page 8 of 88 | May 2010
26
29
31
32
33
34
35
36
37
38
45
46
47
48
51
52
53
54
27
28
30
39
40
41
42
43
44
49
50
55
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events shown in
• CEC interrupt pending register (IPEND) — The IPEND
• SIC interrupt mask registers (SIC_IMASKx) — Control the
written while in supervisor mode. (Note that general-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, that peripheral event is
Default
Core Interrupt ID SIC Registers
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
0
0
0
3
3
3
3
3
4
6
6
6
0
Table 3 on Page
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR5
IAR5
IAR5
IAR5
IAR5
IAR5
IAR5
IAR5
IAR6
IAR6
IAR6
IAR6
IAR6
IAR6
IAR6
IAR6
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
7.