ADSP-BF527KBCZ-6 Analog Devices Inc, ADSP-BF527KBCZ-6 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF527KBCZ-6
• Description: ADSP-BF527 Processor,600Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI CONTROLLER INTERFACE
The processors include a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is compatible with the widely used
I
simultaneous master and slave operation and support for both
7-bit addressing and multimedia data arbitration. The TWI
interface utilizes two pins for transferring clock (SCL) and data
(SDA) and supports the protocol at speeds up to 400k bits/sec.
The TWI interface pins are compatible with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
10/100 ETHERNET MAC
The ADSP-BF526 and ADSP-BF527 processors offer the capa-
bility to directly connect to a network by way of an embedded
Fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)
operation. The 10/100 Ethernet MAC peripheral on the proces-
sor is fully compliant to the IEEE 802.3-2002 standard and it
provides programmable features designed to minimize supervi-
sion, bus use, or message processing by the rest of the processor
system.
Some standard features are:
Some advanced features are:
2
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
C
• Support of MII and RMII protocols for external PHYs.
• Full duplex and half duplex modes.
• Data framing and encapsulation: generation and detection
• Media access management (in half-duplex operation): col-
• Flow control (in full-duplex operation): generation and
• Station management: generation of MDC/MDIO frames
• Operating range for active and sleep operating modes, see
• Internal loopback from Tx to Rx.
• Buffered crystal output to external PHY for support of a
• Automatic checksum computation of IP header and IP
• Independent 32-bit descriptor-driven Rx and Tx DMA
®
of preamble, length padding, and FCS.
lision and contention handling, including control of
retransmission of collision frames and of back-off timing.
detection of PAUSE frames.
for read-write access to PHY registers.
Table 57 on Page 67
single crystal system.
payload fields of Rx frames.
channels.
bus standard. The TWI module offers the capabilities of
and
Table 58 on Page
67.
Rev. B | Page 12 of 88 | May 2010
PORTS
Because of the rich set of peripherals, the processor groups the
many peripheral signals to four ports—Port F, Port G, Port H,
and Port J. Most of the associated pins are shared by multiple
signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 48 bidirectional, general-purpose I/O (GPIO)
pins allocated across three separate GPIO modules—PORTFIO,
PORTGIO, and PORTHIO, associated with Port F, Port G, and
Port H, respectively. Port J does not provide GPIO functional-
ity. Each GPIO-capable pin shares functionality with other
processor peripherals via a multiplexing scheme; however, the
GPIO functionality is the default state of the device upon
power-up. Neither GPIO output nor input drivers are active by
default. Each general-purpose port pin can be individually con-
trolled by manipulation of the port control, status, and interrupt
registers:
• Frame status delivery to memory via DMA, including
• Tx DMA support for separate descriptors for MAC header
• Convenient frame alignment modes support even 32-bit
• Programmable Ethernet event interrupt supports any com-
• 47 MAC management statistics counters with selectable
• Programmable Rx address filters, including a 64-bin
• Advanced power management supporting unattended
• System wakeup from sleep operating mode upon magic
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, seven unused pins may be configured
frame completion semaphores, for efficient buffer queue
management in software.
and payload to eliminate buffer copy operations.
alignment of encapsulated Rx or Tx IP packet data in mem-
ory after the 14-byte MAC header.
bination of:
clear-on-read behavior and programmable interrupts on
half maximum value.
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
transfer of Rx and Tx frames and status to/from external
memory via DMA during low power sleep mode.
packet or any of four user-definable wakeup frame filters.
as GPIO pins for other purposes.
• Any selected Rx or Tx frame status conditions.
• PHY interrupt condition.
• Wake-up frame detected.
• Any selected MAC management counter(s) at half-
• DMA descriptor error.
full.