ADSP-BF527KBCZ-6 Analog Devices Inc, ADSP-BF527KBCZ-6 Datasheet - Page 20

• Manufacturer Part Number: ADSP-BF527KBCZ-6
• Description: ADSP-BF527 Processor,600Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Fourth Byte for Large Page Devices
Bit
D1:D0 Page Size
D2
D5:D4 Block Size
D6
D3, D7 Not Used for configuration
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
• Boot from 8-Bit Host DMA (BMODE = 0xF) — In this
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the Host DMA Port. After completing the
configuration, the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host's responsibility to ensure that valid code has been
placed at this address. The routine at 0xFFA0 0000 can be a
simple initialization routine to configure internal
resources, such as the SDRAM controller, which then
returns using an RTS instruction. The routine may also by
the final application, which will never return to the boot
kernel.
mode, the Host DMA port is configured in 8-bit interrupt
mode, with little endian data formatting. Unlike other
modes, the host is responsible for interpreting the boot
stream. It writes data blocks individually into the Host
DMA port. Before configuring the DMA settings for each
block, the host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the Host DMA Port. The host will receive an
interrupt from the HOST_ACK signal every time it is
allowed to send the next FIFO depths worth (sixteen 32-bit
words) of information. When the host sends an HIRQ con-
trol command, the boot kernel issues a CALL instruction to
address 0xFFA0 0000. It is the host's responsibility to
ensure valid code has been placed at this address. The rou-
tine at 0xFFA0 0000 can be a simple initialization routine
to configure internal resources, such as the SDRAM con-
troller, which then returns using an RTS instruction. The
routine may also by the final application, which will never
return to the boot kernel.
Parameter
(excluding spare area)
Spare Area Size
(excluding spare area)
Bus width
Value
00
01
10
11
00
01
00
01
10
11
00
01
16 byte/512 byte
8 byte/512 byte
not supported
128K byte
256K byte
512K byte
Meaning
64K byte
1K byte
2K byte
4K byte
8K byte
Rev. B | Page 20 of 88 | May 2010
x8
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even dis-
abled based on OTP programming. External hardware,
especially booting hosts, may watch the HWAIT signal to deter-
mine when the pre-boot has finished and the boot kernel starts
the boot process. By programming OTP memory, the user can
also instruct the pre-boot routine to customize the PLL, Internal
Voltage Regulator (ADSP-BF523/ADSP-BF525/ADSP-BF527
only), SDRAM Controller, and Asynchronous Memory
Controller.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass the pre-boot routine and/or boot
kernel in case of a software reset. They can also be used to simu-
late a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the SDRAM controller or to speed up booting by managing the
PLL, clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function that can be
called by the user application at run time. This enables second-
stage boot or boot management schemes to be implemented
with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and super-
visor (O/S kernel, device drivers, debuggers, ISRs) modes
of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
• A multi-issue load/store modified-Harvard architecture,
both 8-bit and 16-bit operations.
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.