SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 84

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
Port 1 (P10–P17)
AD[8:15] bits of the address/data bus or the A[8:15] bits of the address bus. The P1CR and P1FC registers
select the direction and function of the Port 1 pins. Upon reset, the Output Latch (P1) is cleared, and the
P1CR and P1FC register bits are cleared to all 0s, configuring all Port 1 pins as input port pins.
Eight Port 1 pins can be individually programmed to function as discrete general-purpose I/O pins, the
For external memory accesses, Port 1 pins must be configured as AD[8:15] or A[8:15].
Direction Control
Function Control
Output Latch
P1CR Write
P1FC Write
P1 Write
(bitwise)
(bitwise)
Reset
Figure 7.3 Port 1 (P10–P17)
TMP1940CYAF-42
P1 Read
Output Buffer
TMP1940CYAF
Port 1
P10–P17
(AD8–AD15/A8–A15)