SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 73

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
Interrupt Sources
The TMP1940CYAF provides a reset interrupt, nonmaskable interrupts, and maskable interrupts:
on-chip Watchdog Timer (WDT) is also capable of being a source of a nonmaskable interrupt
(INTWDT). Reset and nonmaskable interrupts are always vectored to virtual address 0xBFC0_0000.
Maskable interrupts are vectored to virtual addresses 0xBFC0_0210 through 0xBFC0_0260, as shown
below.
Reset and nonmaskable interrupts
Maskable interrupts
The RESET pin causes a Reset interrupt. The NMI pin functions as a nonmaskable interrupt. The
The TMP1940CYAF supports two types of maskable interrupts: software and hardware interrupts.
Note 1:
Note 2:
Reset
Nonmaskable
Software
Hardware
Interrupt Source
The above table shows the vector addresses when the BEV bit in the CP0 Status
register is set to 1. When BEV=1, all exception vectors reside in the on-chip ROM
space.
Software interrupts are posted by setting one of the Sw[3:0] bits in the CP0 Cause
register. Software interrupts are distinct from the “Software Set” interrupt which is one
of the hardware interrupt sources. A Software Set interrupt is posted from the INTC to
the TX19 core processor when the IL0[2:0] field in the INTC’s IMC0 register is set to a
non-zero value.
Swi0
Swi1
Swi2
Swi3
TMP1940CYAF-31
0xBFC0_0000
0xBFC0_0210
0xBFC0_0220
0xBFC0_0230
0xBFC0_0240
0xBFC0_0260
Virtual Vector Address
TMP1940CYAF