SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 219

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.12 Signal Generation Timing
(1) UART Mode
(2) I/O Interface Mode
Receive Operation
Transmit Operation
Interrupt
Framing Error
Parity Error
Overrun Error
Interrupt
Transmit
Interrupt
Receive Interrupt
Note 1:
Note 2:
Don’t disable receive operations by clearing the SC0MOD0.RXE bit while any character is
Don’t modify any control register during transmit or receive operations.
being received.
SCLK Output Mode
SCLK Input Mode
SCLK Output Mode
SCLK Input Mode
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., bit 8)
Immediately before
the stop bit is shifted
out
TMP1940CYAF-177
9 Data Bits
9 Data Bits
Immediately after the rising edge of the last SCLK pulse (See Figure
13.29)
Immediately after the rising or falling edge of the last SCLK pulse,
as programmed (See Figure 13.30)
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.31)
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.32)
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., parity bit)
Middle of the last bit
(i.e., parity bit)
Immediately before the
stop bit is shifted out
8 Data Bits with
8 Data Bits with
Parity
Parity
TMP1940CYAF
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., parity bit)
Middle of the stop bit
Immediately before the stop bit
is shifted out
8 Data Bits with No Parity
7 Data Bits with No Parity
8 Data Bits with No Parity
7 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with Parity