SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 53

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.
(Selectable peripheral operation)
Note 1: Before a transition to SLOW or SLEEP mode can occur, the low-speed oscillator (fs) must be oscillating
Note 2: After SLEEP mode is exited, the TMP1940CYAF returns to the mode it was in before entering SLEEP mode.
Note 3: After STOP mode is exited, the TMP1940CYAF returns to the mode specified by the System Control Register
Clock/Standby Control
supplied from the X1/X2 pins, and Dual-Clock mode which operates off of the high-speed clock supplied from
the X1/X2 pins and the low-speed clock supplied from the XT1/XT2 pins.
(Selectable peripheral operation)
The TMP1940CYAF has two clocking modes: Single-Clock mode which operates off of the high-speed clock
Figure 5.1 shows the transitions between clocking modes in Single-Clock mode and Dual-Clock mode.
(CPU halted)
IDLE Mode
(Only RTC is active.)
stably.
0 (SYSCR0). See Section 5.2.
(CPU halted)
IDLE Mode
SLEEP Mode
(fs only)
A. When the PLL clock is used
fosc:
fs:
fpll:
fc:
fgear:
fsys:
fperiph:
fc
NORMAL Mode
Figure 5.2 Default Clock Frequencies in NORMAL Mode
fperiph
fsys
fsys
fpll
Reset
Clock frequency supplied via the X1 and X2 pins
Clock frequency supplied via the XT1 and XT2 pins
PLL multiplied clock frequency (x4)
Clock frequency selected by the PLLOFF pin
Clock frequency selected by the GEAR[1:0] bits in the SYSCR1
System clock frequency selected by the SYSCK bit in the SYSCR1
Clock source for the prescalers inside on-chip peripherals
fosc / 2
fosc
fc / 8
Instruction
Reset released
PLLOFF = 1
PLL used
Figure 5.1 Standby Modes Flow Diagram
fsys
Instruction
Instruction
Interrupt
Interrupt
4
Instruction
Interrupt
Interrupt
(a) Single-Clock Mode
(b) Dual-Clock Mode
TMP1940CYAF-11
NORMAL Mode
(fc/gear_value)
SLOW Mode
(fc / gear_value)
NORMAL Mode
Reset
(fs)
Reset
B. When the PLL is not used
Reset released
Reset released
NORMAL Mode
fperiph
fsys
Interrupt
fc
fsys
Reset
fosc / 2
Instruction
Interrupt
fosc / 16
Instruction
fc / 8
Interrupt
Reset released
PLLOFF = 0
PLL not used
fsys
TMP1940CYAF
Instruction
(Whole chip halted)
(Whole chip halted)
STOP Mode
STOP Mode